SC.mesa ///StdCell/SC.mesa
Copyright © 1985, 1986 by Xerox Corporation. All rights reserved.
Last Edited by: Preas, November 7, 1985 10:11:48 am PST
DIRECTORY
CD,
Core,
D2Basic,
Properties,
Rope,
Route,
RTBasic;
SC: CEDAR DEFINITIONS = BEGIN
Theory
This interface defines the basic data structures and procedures to define a standard cell object from a Core description.
Common Types
RopeList: TYPE = LIST OF Rope.ROPE;
Layer: TYPE = CD.Layer;
Rect: TYPE = D2Basic.Rect;
RefRect: TYPE = REF Rect;
Pos: TYPE = D2Basic.Pos;
Number: TYPE = D2Basic.Number;
SideOrNone: TYPE = RTBasic.SideOrNone;
Side: TYPE = RTBasic.Side;
DirectionOrNone: TYPE = RTBasic.DirectionOrNone;
Direction: TYPE = RTBasic.Direction;
PropList: TYPE = Properties.PropList;
Errors
Error: ERROR [errorType: ErrorType ← callingError, explanation: Rope.ROPE ← NIL];
Signal: SIGNAL [signalType: ErrorType ← callingError, explanation: Rope.ROPE ← NIL];
ErrorType: TYPE = {programmingError, callingError, noResource, other};
Design Rules
DesignRules: TYPE = REF DesignRulesRec;
DesignRulesRec:
TYPE =
RECORD[
horizLayer, vertLayer: Rope.ROPE,
rowRules, sideRules: Route.DesignRules,
technology: PRIVATE REF ANY ← NIL,
properties: PropList ← NIL];
CreateDesignRules:
PROC [technologyKey:
ATOM, horizLayer, vertLayer: Rope.
ROPE, rowDirection: Direction, properties: PropList ←
NIL]
RETURNS [designRules: DesignRules];
Define the standard cell design rules. technologyKey values must correspond to one of the ChipNDale technologies. horizLayer, vertLayer should be "poly", "metal" or "metal2".
StdCell Design
Handle: TYPE = REF HandleRec;
HandleRec:
TYPE =
RECORD [
name: Rope.ROPE ← NIL,
coreCellType: Core.CellType ← NIL,
rules: DesignRules ← NIL,
properties: PropList ← NIL,
parms: PRIVATE REF ANY ← NIL,
structureData: PRIVATE REF ANY ← NIL,
layoutData: PRIVATE REF ANY ← NIL];
Result: TYPE = REF ResultRec;
ResultRec:
TYPE =
RECORD[
handle: Handle,
object: CD.Object,
rect: Rect ← [0, 0, 0, 0],
polyLength, metalLength, metal2Length, polyToMetal, metalToMetal2: NAT ← 0,
numIncompletes: NAT ← 0,
incompleteNets: RopeList ← NIL];
CreateHandle:
PROC [cellType: Core.CellType, cdDesign, libDesign:
CD.Design, designRules: DesignRules, name: Rope.
ROPE ←
NIL, properties: PropList ←
NIL]
RETURNS [handle: Handle];
Create a StdCellHandle. The StdCellHandle definition includes the design rules (conductor and via widths and spacings) for the routing channels as well as the circuit structure definition.
unconnectedProp:
ATOM;
Core does not permit pins to be unconnected; this is a problem!
unconnected pins are signified by attaching them to a net with the unconnectedProp property.
Standard Cell Optimization and Construction
The following operations are available for a standard cell design.
InitialPlace:
PROC [handle: Handle, numRows:
NAT ← 0];
Determine an initial placement for the instances.
PosImprove:
PROC [handle: Handle, maxCycles:
INT ← 5];
Improve the positions of instances whithin rows.
OrientImprove:
PROC [handle: Handle, maxCycles:
INT ← 5];
Improve the orientation of instances.
PlaceImprove:
PROC [handle: Handle, t0:
REAL ← 100000.0, alpha:
REAL ← 0.98, eqVarLimit:
REAL ← 0.10, fzVarLimit:
REAL ← 0.02, eqTabSize, fzTabSize:
INT ← 200, seed:
INT ← 0];
Improve the placement for the instances.
GlobalRoute:
PROC [handle: Handle];
Determine strategic paths for the wiring that must cross cell rows.
DetailRoute:
PROC [handle: Handle]
RETURNS [result: Result];
Determine actual wiring paths. Create a ChipNDale object and include the placement and routing in the object. This object will be included in design if design # NIL (form CreateHandle).
Clean Up
Destroy:
PROC [handle: Handle];
Remove circular references so garbage collection can work
Sugar
CreateLayout:
PROC [technologyKey:
ATOM, horizLayer, vertLayer: Rope.
ROPE, rowDirection: Direction, numRows:
NAT, cellType: Core.CellType, cdDesign, libDesign:
CD.Design ←
NIL, name: Rope.
ROPE ←
NIL, properties: PropList ←
NIL]
RETURNS [object:
CD.Object];
Create a standard cell object by performing the above operations
END.