BEGIN
c1, c2, d1, d2: Route.Pin;
c1cd, c2cd, d1cd, d2cd: CD.Instance;
cProperties: Route.PropList ← NIL;
result: Route.RoutingResult;
design: CD.Design;
object: CD.Object;
technology: CD.Technology ← CD.FetchTechnology[$cmos];
metal: Route.Layer ← CD.FetchLayer[technology, $met];
metal2: Route.Layer ← CD.FetchLayer[technology, $met2];
rules: Route.DesignRules ← Route.CreateDesignRules[$cmos, metal, metal2, horizontal];
routingArea: Route.RoutingArea ← Route.CreateRoutingArea["RouteTestC", rules];
Route.IncludeRoutingAreaSide[routingArea, bottom, [0, 0]];
Route.IncludeRoutingAreaSide[routingArea, top, [0, 0]];
cProperties ← RouteUtil.PutNumberProp[cProperties, Route.trunkWidthKey, 20];
cProperties ← RouteUtil.PutNumberProp[cProperties, Route.branchWidthKey, 20];
c1cd ← RouteUtil.CreateCDPin["c1", [60, 0, 64, -4], metal2];
c1 ← Route.CreatePin[c1cd, bottom];
c2cd ← RouteUtil.CreateCDPin["c1", [134, 0, 138, 4], metal2];
c2 ← Route.CreatePin[c2cd, top];
Route.IncludeNet[routingArea, "c", LIST[c1, c2], cProperties];
d1cd ← RouteUtil.CreateCDPin["d1", [134, 0, 138, -4], metal2];
d1 ← Route.CreatePin[d1cd, bottom];
d2cd ← RouteUtil.CreateCDPin["d2", [100, 0, 104, 4], metal2];
d2 ← Route.CreatePin[d2cd, top];
Route.IncludeNet[routingArea, "d", LIST[d1, d2]];
result ← Route.ChannelRoute[routingArea, [[0, 0], [200, 0], [0, 30], [0,0]], [0, 0, 200, 30], full];
design ← CDOps.CreateDesign[technology];
object ← Route.RetrieveRouting[result, result.routingArea.name, NIL, NIL].object;
[ ] ← CDCells.IncludeOb[design: design,
cell: NIL, ob: object, position: [0, 0], orientation: 0,
cellCSystem: interrestCoords, obCSystem: interrestCoords, mode: dontPropagate];
IF
CDIO.WriteDesign[design, result.routingArea.name]
THEN
BEGIN
newCellName: Rope.ROPE ← CDDirectory.Name[object];
IF ~Rope.Equal[result.routingArea.name, newCellName]
THEN
TerminalIO.WriteRope[Rope.Cat["cell name changed to: ", newCellName, "\n"]];
END
ELSE
TerminalIO.WriteRope["Error: design not written\n"];
END.