CD,

CDCells,

CDDirectory,

CDIO,

CDOps,

Rope,

Route,

RouteUtil,

TerminalIO;

IMPORTS CD, CDCells, CDDirectory, CDIO, CDOps, Rope, Route, RouteUtil, TerminalIO

SHARES Route =

BEGIN

a1, a2, a3, a4, b1, b2, c1, c2, d1, d2, e1, e2, f1, f2, f3, f4, f5, g1, g2, h1, h2: Route.Pin;

a1cd, a2cd, a3cd, a4cd, b1cd, b2cd, c1cd, c2cd, d1cd, d2cd, e1cd, e2cd, f1cd, f2cd, f3cd, f4cd, f5cd, g1cd, g2cd, h1cd, h2cd: CD.Instance;

result: Route.RoutingResult;

design: CD.Design;

object: CD.Object;

technology: CD.Technology ← CD.FetchTechnology[$cmos];

metal: Route.Layer ← CD.FetchLayer[technology, $met];

metal2: Route.Layer ← CD.FetchLayer[technology, $met2];

rules: Route.DesignRules ← Route.CreateDesignRules[$cmos, metal, metal2, horizontal];

routingArea: Route.RoutingArea ← Route.CreateRoutingArea["RouteTest", rules];

Route.IncludeRoutingAreaSide[routingArea, bottom, [0, 0]];

Route.IncludeRoutingAreaSide[routingArea, top, [0, 0]];

Route.IncludeRoutingAreaSide[routingArea, left, [0, 0]];

a1cd ← RouteUtil.CreateCDPin["a1", [6, 0, 10, -8], metal2];

a1 ← Route.CreatePin[a1cd, bottom];

a2cd ← RouteUtil.CreateCDPin["a2", [24, 0, 28, 8], metal2];

a2 ← Route.CreatePin[a2cd, top];

a3cd ← RouteUtil.CreateCDPin["a3", [44, 0, 48, 8], metal2];

a3 ← Route.CreatePin[a3cd, top];

a4cd ← RouteUtil.CreateCDPin["a4", [0, 0, 0, 0], metal];

a4 ← Route.CreatePin[a4cd, left];

Route.IncludeNet[routingArea, "a", LIST[a1, a2, a3, a4]];

b1cd ← RouteUtil.CreateCDPin["b1", [24, 0, 28, -8], metal2];

b1 ← Route.CreatePin[b1cd, bottom];

b2cd ← RouteUtil.CreateCDPin["b2", [82, 0, 86, 8], metal2];

b2 ← Route.CreatePin[b2cd, top];

Route.IncludeNet[routingArea, "b", LIST[b1, b2]];

c1cd ← RouteUtil.CreateCDPin["c1", [123, 0, 127, -8], metal2];

c1 ← Route.CreatePin[c1cd, bottom];

c2cd ← RouteUtil.CreateCDPin["c2", [146, 0, 150, 8], metal2];

c2 ← Route.CreatePin[c2cd, top];

Route.IncludeNet[routingArea, "c", LIST[c1, c2]];

d1cd ← RouteUtil.CreateCDPin["d1", [146, 0, 150, -8], metal2];

d1 ← Route.CreatePin[d1cd, bottom];

d2cd ← RouteUtil.CreateCDPin["d2", [123, 0, 127, 8], metal2];

d2 ← Route.CreatePin[d2cd, top];

Route.IncludeNet[routingArea, "d", LIST[d1, d2]];

e1cd ← RouteUtil.CreateCDPin["e1", [44, 0, 48, -8], metal2];

e1 ← Route.CreatePin[e1cd, bottom];

e2cd ← RouteUtil.CreateCDPin["e2", [100, 0, 104, 8], metal2];

e2 ← Route.CreatePin[e2cd, top];

Route.IncludeNet[routingArea, "e", LIST[e1, e2]];

f1cd ← RouteUtil.CreateCDPin["f1", [62, 0, 66, -8], metal2];

f1 ← Route.CreatePin[f1cd, bottom];

f2cd ← RouteUtil.CreateCDPin["f2", [166, 0, 170, 8], metal2];

f2 ← Route.CreatePin[f2cd, top];

f3cd ← RouteUtil.CreateCDPin["f3", [62, 0, 70, 8], metal2];

f3 ← Route.CreatePin[f3cd, top];

f4cd ← RouteUtil.CreateCDPin["f4", [166, 0, 170, -8], metal2];

f4 ← Route.CreatePin[f4cd, bottom];

f5cd ← RouteUtil.CreateCDPin["f5", [0, 0, 0, 0], metal];

f5 ← Route.CreatePin[f5cd, right];

Route.IncludeNet[routingArea, "f", LIST[f1, f2, f3, f4, f5]];

g1cd ← RouteUtil.CreateCDPin["g1", [212, 0, 216, -8], metal2];

g1 ← Route.CreatePin[g1cd, bottom];

g2cd ← RouteUtil.CreateCDPin["g1", [238, 0, 242, 8], metal2];

g2 ← Route.CreatePin[g2cd, top];

Route.IncludeNet[routingArea, "g", LIST[g1, g2]];

h1cd ← RouteUtil.CreateCDPin["h1", [238, 0, 242, -8], metal2];

h1 ← Route.CreatePin[h1cd, bottom];

h2cd ← RouteUtil.CreateCDPin["h2", [212, 0, 216, 8], metal2];

h2 ← Route.CreatePin[h2cd, top];

Route.IncludeNet[routingArea, "h", LIST[h1, h2]];

result ← Route.ChannelRoute[routingArea, [[0, 0], [250, 0], [0, 30], [-10, 0]], [0, 0, 250, 30], full];

design ← CDOps.CreateDesign[technology];

object ← Route.RetrieveRouting[result, result.routingArea.name, NIL, NIL].object;

[ ] ← CDCells.IncludeOb[design: design,

IF CDIO.WriteDesign[design, result.routingArea.name] THEN

ELSE

END.