<> <> <> <<>> DIRECTORY CoreCreate; SSI: CEDAR DEFINITIONS = BEGIN OPEN CoreCreate; <<>> <<"Vdd", "Gnd", "Input", "nOutput">> Inverter: PROC [w: NAT _ 4, r: REAL _ 2.5] RETURNS [ct: CellType]; <<>> <<"Vdd", "Gnd", "Input", "Drive", "nDrive", "nOutput">> TristateBuffer: PROC [w: NAT _ 4, r: REAL _ 2.5] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["Input", i], "nOutput">> NAnd: PROC [i: NAT _ 2, w: NAT _ 4, r: REAL _ 2.5] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["Input", i], "Output">> And: PROC [i: NAT _ 2, w: NAT _ 4, r: REAL _ 2.5] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["Input", i], "nOutput">> NOr: PROC [i: NAT _ 2, w: NAT _ 4, r: REAL _ 2.5] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["Input", i], "Output">> Or: PROC [i: NAT _ 2, w: NAT _ 4, r: REAL _ 2.5] RETURNS [ct: CellType]; END.