<> <> <> <<>> DIRECTORY Core, CoreClasses, Ports; Rosemary: CEDAR DEFINITIONS = BEGIN ROPE: TYPE = Core.ROPE; <> BindCellType: PROC [cellType: Core.CellType, roseClassName: ROPE] RETURNS [sameCellType: Core.CellType]; BindCellClass: PROC [cellClass: Core.CellClass, roseClassName: ROPE] RETURNS [sameCellClass: Core.CellClass]; Register: PROC [roseClassName: ROPE, init: InitProc _ NIL, evalSimple: EvalProc _ NIL] RETURNS [sameRoseClassName: ROPE]; InitProc: TYPE = PROC [cellType: Core.CellType, p: Ports.Port] RETURNS [stateAny: REF ANY _ NIL]; <> <<>> StateCopyProc: TYPE = PROC [from: REF ANY, to: REF ANY]; <> <<>> EvalProc: TYPE = PROC [p: Ports.Port, stateAny: REF ANY]; <> Stop: SIGNAL [msg: ROPE _ NIL, data: REF ANY _ NIL]; <> <> AddCutSets: PROC [cellType: Core.CellType, cs1, cs2, cs3, cs4, cs5, cs6: ROPE _ NIL] RETURNS [sameCellType: Core.CellType]; <> SetFixedWire: PROC [wire: Core.Wire, level: Ports.Level] RETURNS [sameWire: Core.Wire]; <> SetWireSize: PROC [wire: Core.Wire, size: WireSize] RETURNS [sameWire: Core.Wire]; <> <<>> WireSize: TYPE = Ports.Drive[chargeWeak..chargeStrong]; SetTransistorCellTypeSize: PROC [transistor: Core.CellType, size: TransistorSize] RETURNS [sameTransistor: Core.CellType]; <> SetTransistorInstanceSize: PROC [transistor: CoreClasses.CellInstance, size: TransistorSize] RETURNS [sameTransistor: CoreClasses.CellInstance]; <<>> TransistorSize: TYPE = Ports.Drive[driveWeak..driveStrong]; InstantiateCellType: PROC [cellType: Core.CellType, testPort: Ports.Port, statePoints: NAT _ 0] RETURNS [simulation: Simulation]; <> InstantiateInstances: PROC [cellType: Core.CellType, testPort: Ports.Port, cutSet: ROPE _ NIL, statePoints: NAT _ 0] RETURNS [simulation: Simulation]; Initialize: PROC [simulation: Simulation, steady: BOOL _ TRUE]; <> <<>> Settle: PROC [simulation: Simulation, updateProc: UpdateProc _ NIL]; UpdateProc: TYPE = PROC [wire: RoseWire]; <> <<>> <> InstantiationPath: TYPE = LIST OF CoreClasses.CellInstance; -- top level first <<>> GetCellTypeState: PROC [simulation: Simulation] RETURNS [stateAny: REF ANY]; <> <<>> GetInstanceState: PROC [simulation: Simulation, instantiationPath: InstantiationPath, instance: CoreClasses.CellInstance] RETURNS [stateAny: REF ANY]; <> <<>> GetWireValue: PROC [simulation: Simulation, instantiationPath: InstantiationPath, wire: Core.Wire, container: Ports.LevelSequence]; <> StatePoint: PROC [simulation: Simulation, point: NAT]; <> RestoreState: PROC [simulation: Simulation, point: NAT]; <> <> <> <<>> GetCellType: PROC [rootCellType: Core.CellType, path: PackedPath] RETURNS [cellType: Core.CellType _ NIL]; Recordify: PROC [ct: Core.CellType] RETURNS [rc: Core.CellType]; <> <> <<>> <> <> < 16 words/transistor>> < 32 words/wire + quantization of RoseTransistorSeq>> <> <<>> RoseCellType: TYPE = REF RoseCellTypeRec; RoseCellTypeRec: TYPE = RECORD [ evalSimple: EvalProc _ NIL, init: InitProc _ NIL, copy: StateCopyProc _ NIL]; Simulation: TYPE = REF SimulationRec; SimulationRec: PUBLIC TYPE = RECORD [ coreCellType: Core.CellType _ NIL, cutSet: ROPE _ NIL, coreToRoseWires: ARRAY HashIndex OF RoseWire _ ALL[NIL], coreToRoseInstances: ARRAY HashIndex OF RoseCellInstance _ ALL[NIL], coreToValues: ValueBindings _ NIL, instanceNeedEval: RoseCellInstance _ NIL, perturbed: RoseWire _ NIL, roseBoolWires: LIST OF RoseWire _ NIL, publicBindings: PortBindings _ NIL, scratchValue: Ports.LevelSequence _ NIL, scratchDrive: DriveSequence _ NIL, vicinityByStrength: ARRAY Ports.Drive OF VicinityRec, testPort: Ports.Port _ NIL, statePoints: PortSequence _ NIL]; HashIndex: TYPE = [0..512); DriveSequence: TYPE = REF DriveRec; DriveRec: TYPE = RECORD [drives: SEQUENCE size: CARDINAL OF Ports.Drive]; VicinityRec: TYPE = RECORD[ wires: RoseWires, firstFree: CARDINAL _ 0]; PortSequence: TYPE = REF PortSequenceRec; PortSequenceRec: TYPE = RECORD [ports: SEQUENCE size: NAT OF Ports.Port]; RoseCellInstance: TYPE = REF RoseCellInstanceRec; RoseCellInstanceRec: TYPE = RECORD [ nextNeedEval: RoseCellInstance _ NIL, roseCellType: RoseCellType _ NIL, publicPort: Ports.Port _ NIL, portBindings: PortBindings _ NIL, state: REF ANY _ NIL, statePoints: SRA _ NIL, path: PackedPath, instance: CoreClasses.CellInstance _ NIL, nextBucket: RoseCellInstance _ NIL]; SRA: TYPE = REF SRASeq; SRASeq: TYPE = RECORD [elements: SEQUENCE size: CARDINAL OF REF ANY]; PortBindings: TYPE = REF PortBindingSeq; PortBindingSeq: TYPE = RECORD [elements: SEQUENCE size: CARDINAL OF PortBinding]; PortBinding: TYPE = REF PortBindingRec; PortBindingRec: TYPE = RECORD [ instance: RoseCellInstance _ NIL, clientPort: Ports.Port _ NIL, fields: Fields _ NIL, currentDrive: Ports.Drive _ none, statePoints: DriveSequence _ NIL]; Fields: TYPE = REF FieldSeq; FieldSeq: TYPE = RECORD [elements: SEQUENCE size: CARDINAL OF Field]; Field: TYPE = REF FieldRec; FieldRec: TYPE = RECORD [ portBinding: PortBinding _ NIL, portStartBit: NAT _ 0, roseWire: RoseWire _ NIL, currentValue: Ports.LevelSequence _ NIL, statePoints: LevelSequenceSeq _ NIL]; RoseWires: TYPE = REF RoseWireSeq; RoseWireSeq: TYPE = RECORD [elements: SEQUENCE size: CARDINAL OF RoseWire]; RoseWire: TYPE = REF RoseWireRec; RoseWireRec: TYPE = RECORD [ connections: Fields _ NIL, currentValue: Ports.LevelSequence _ NIL, < the wire is atomic. The following fields are only significant if the wire is atomic.>> nextPerturbedWire: RoseWire _ NIL, previousPerturbedWire: RoseWire _ NIL, nextRecomputed: RoseWire _ NIL, channels: RoseTransistors _ NIL, gates: RoseTransistors _ NIL, connectionDrive: Ports.Drive _ none, switchDrive: Ports.Drive _ none, upDrive: Ports.Drive _ none, downDrive: Ports.Drive _ none, wireDrive: Ports.Drive _ charge, connectionLevel: Ports.Level _ L, wireLevel: Ports.Level _ L, mark: BOOL _ FALSE, statePoints: REF ANY _ NIL, -- TypeUnion[Ports.LevelSequence, LevelSequenceSeq] path: PackedPath, wire: Core.Wire, nextBucket: RoseWire _ NIL]; LevelSequenceSeq: TYPE = REF LevelSequenceSeqRec; LevelSequenceSeqRec: TYPE = RECORD [elements: SEQUENCE size: CARDINAL OF Ports.LevelSequence]; RoseTransistors: TYPE = REF RoseTransistorSeq; RoseTransistorSeq: TYPE = RECORD [elements: SEQUENCE size: CARDINAL OF RoseTransistor]; RoseTransistor: TYPE = REF RoseTransistorRec; RoseTransistorRec: TYPE = RECORD [ gate: RoseWire _ NIL, ch1: RoseWire _ NIL, ch2: RoseWire _ NIL, conductivity: Ports.Drive _ drive, type: CoreClasses.TransistorType _ nE]; PackedPath: TYPE = RECORD [ length: PathIndex _ 0, bits: PACKED ARRAY PathIndex OF BOOL _ ALL[FALSE]]; PathIndex: TYPE = [0..32); ValueBindings: TYPE = LIST OF ValueBinding; ValueBinding: TYPE = RECORD [ path: PackedPath, wire: Core.Wire _ NIL, values: Values _ NIL]; Values: TYPE = LIST OF Value; Value: TYPE = RECORD [ roseWire: RoseWire _ NIL, firstBit: NAT _ 0, size: NAT _ 0]; <<>> END.