RoseDebug.mesa
Copyright © 1985 by Xerox Corporation. All rights reserved.
Barth, March 25, 1986 9:59:11 am PST
Bertrand Serlet March 18, 1986 3:39:48 pm PST
DIRECTORY Core, CoreClasses, CoreOps, Commander, IO, Ports, ProcessProps, RefTab, Rosemary;
RoseDebug: CEDAR PROGRAM
IMPORTS CoreOps, IO, Ports, ProcessProps, RefTab, Rosemary
EXPORTS
= BEGIN OPEN Rosemary;
NeedEval: PROC [simulation: Simulation, out: Core.STREAM ← NIL] = {
IF out=NIL THEN out ← NARROW[ProcessProps.GetProp[$CommanderHandle], Commander.Handle].out;
IF simulation.perturbed#NIL THEN FOR roseWire: RoseWire ← simulation.perturbed, roseWire.nextPerturbedWire DO
ct: Core.CellType ← GetCellType[simulation.coreCellType, roseWire.path];
rct: CoreClasses.RecordCellType ← NARROW[ct.data];
IO.PutF[out, "%g ", IO.rope[CoreOps.GetFullWireNames[rct.internal, roseWire.wire].first]];
IF roseWire=simulation.perturbed.previousPerturbedWire THEN EXIT;
ENDLOOP;
};
EnumerateRoseWires: PROC [simulation: Simulation] RETURNS [roseWires: LIST OF RoseWire ← NIL] = {
FOR hash: HashIndex IN HashIndex DO
FOR roseWire: RoseWire ← simulation.coreToRoseWires[hash], roseWire.nextBucket UNTIL roseWire=NIL DO
roseWires ← CONS[roseWire, roseWires];
ENDLOOP;
ENDLOOP;
};
FindCoreWires: PROC [simulation: Simulation, wire: Core.Wire] RETURNS [roseWires: LIST OF RoseWire ← NIL] = {
FOR hash: HashIndex IN HashIndex DO
FOR roseWire: RoseWire ← simulation.coreToRoseWires[hash], roseWire.nextBucket UNTIL roseWire=NIL DO
IF roseWire.wire=wire THEN roseWires ← CONS[roseWire, roseWires];
ENDLOOP;
ENDLOOP;
};
Print: PROC [simulation: Simulation, out: Core.STREAM ← NIL] = {
Drive: PROC [drive: Ports.Drive] RETURNS [IO.Value] = {
RETURN[IO.rope[SELECT drive FROM
expect => "e",
none => "n",
chargeWeak => "cw",
chargeMediumWeak => "cmw",
charge => "c",
chargeMediumStrong => "cms",
chargeStrong => "cs",
force => "f",
driveWeak => "dw",
driveMediumWeak => "dmw",
drive => "d",
driveMediumStrong => "dms",
driveStrong => "ds",
infinite => "i",
ENDCASE => ERROR]];
};
Level: PROC [level: Ports.Level] RETURNS [IO.Value] = {
RETURN[IO.rope[SELECT level FROM
L => "L",
H => "H",
X => "X",
ENDCASE => ERROR]];
};
PrintTransistor: PROC [trans: RoseTransistor] = {
IF trans#NIL THEN IO.PutF[out, "%g%g%g", IO.int[LOOPHOLE[trans]], IO.rope[SELECT trans.type FROM nE => "n", pE => "p", nD => "d", ENDCASE => ERROR], Drive[trans.conductivity]];
};
PrintTransistors: PROC [trans: RoseTransistors] = {
IF trans#NIL THEN FOR t: NAT IN [0..trans.size) DO
IO.PutRope[out, " "];
PrintTransistor[trans[t]];
[] ← RefTab.Insert[x: tranTab, key: trans[t], val: $Transistor];
ENDLOOP;
};
PrintEachTransistor: RefTab.EachPairAction = {
GetWireName: PROC [roseWire: RoseWire] RETURNS [IO.Value] = {
rc: Core.CellType ← GetCellType[simulation.coreCellType, roseWire.path];
rct: CoreClasses.RecordCellType ← NARROW[rc.data];
RETURN[IO.rope[CoreOps.GetFullWireNames[rct.internal, roseWire.wire].first]];
};
trans: RoseTransistor ← NARROW[key];
quit ← FALSE;
PrintTransistor[trans];
IO.PutF[out, ", gate: %g, ch1: %g, ch2: %g\n", GetWireName[trans.gate], GetWireName[trans.ch1], GetWireName[trans.ch2]];
};
PrintFieldDriveAndVals: PROC [fields: Fields] = {
IF fields#NIL THEN FOR f: NAT IN [0..fields.size) DO
field: Field ← fields[f];
IF field.portBinding.instance#NIL THEN IO.PutF[out, " %g -", IO.rope[CoreOps.GetCellTypeName[ field.portBinding.instance.instance.type]]]
ELSE IO.PutRope[out, " <unknown> -"];
IO.PutF[out, " fd: %g, fv: %g\n", Drive[field.portBinding.currentDrive], IO.rope[Ports.LevelSequenceToRope[field.currentValue, field.currentValue.size]]];
ENDLOOP;
};
tranTab: RefTab.Ref ← RefTab.Create[];
rct: CoreClasses.RecordCellType;
IF out=NIL THEN out ← NARROW[ProcessProps.GetProp[$CommanderHandle], Commander.Handle].out;
FOR hash: HashIndex IN HashIndex DO
FOR roseWire: RoseWire ← simulation.coreToRoseWires[hash], roseWire.nextBucket UNTIL roseWire=NIL DO
rc: Core.CellType ← GetCellType[simulation.coreCellType, roseWire.path];
rct ← NARROW[rc.data];
IF roseWire.currentValue=NIL THEN {
IO.PutFL[out, "%g - cd:%g, sd:%g, ud:%g, dd:%g, wd:%g, cl:%g, wl: %g\n", LIST[IO.rope[CoreOps.GetFullWireNames[rct.internal, roseWire.wire].first], Drive[roseWire.connectionDrive], Drive[roseWire.switchDrive], Drive[roseWire.upDrive], Drive[roseWire.downDrive], Drive[roseWire.wireDrive], Level[roseWire.connectionLevel], Level[roseWire.wireLevel]]];
IO.PutRope[out, " gates:"];
PrintTransistors[roseWire.gates];
IO.PutRope[out, "\n channels:"];
PrintTransistors[roseWire.channels];
IO.PutRope[out, "\n"];
}
ELSE {
ERROR;
};
PrintFieldDriveAndVals[roseWire.connections];
ENDLOOP;
ENDLOOP;
[] ← RefTab.Pairs[tranTab, PrintEachTransistor];
};
END.