DIRECTORY PrincOps, RoseControl, RoseSimTypes, RoseWireTypes; RoseEngine: CEDAR DEFINITIONS = BEGIN OPEN RoseWireTypes, RoseSimTypes; GetWireGroup: PROC [wire: Wire] RETURNS [wg: WireGroup]; ScheduleCell: PROC [cell: RoseCellInstance]; PerturbWire: PROC [rw: RoseWire, agitator: ModelSlot, evenIfInput: BOOL]; GetRoseCell: PROC [sim: Simulation, ci: CellInstance] RETURNS [rci: RoseCellInstance]; GetRoseWire: PROC [sim: Simulation, w: Wire] RETURNS [rw: RoseWire]; GetRoseCellType: PROC [ct: CellType, details, privates: BOOL] RETURNS [rct: RoseCellType]; NoteTweak: PROC [rw: RoseWire, bbTable: PrincOps.BitBltTablePtr]; END. ΄RoseEngine.Mesa Spreitzer, October 18, 1985 5:17:01 pm PDT Barth, August 16, 1985 4:55:42 pm PDT This module defines some random stuff useful in the kernel of the simulator. Κ– "cedar" style˜code™K™*K™%—K˜KšΟk œ4˜=K˜KšΠbx œœ œ˜K˜K™LK˜Kšœœ˜'K˜KšΟn œœœ˜8K˜KšŸ œœ˜,K˜KšŸ œœ2œ˜IK˜KšŸ œœ%œ˜VK˜KšŸ œœœ˜DK˜KšŸœœ#œœ˜ZK˜KšŸ œœ2˜AK˜Kšœ˜—…—‚<