DIRECTORY BasicTime, BitTwiddling, Core, CoreClasses, CoreOps, CoreProperties, GetMe, IO, Rope, RoseBehavior, RoseBind; Agger: CEDAR PROGRAM IMPORTS CoreClasses, CoreOps, CoreProperties, IO, RoseBind = BEGIN OPEN Core, CoreClasses, CoreOps, CoreProperties, RoseBind; MakeLatchPW: PROC [width: NAT] RETURNS [pw: Wire] = { pw _ CreateRecordWire[LIST[ CreateAtomWire["load"], CreateBasicSequenceWire["in", width, NIL, Props[[variableWire, $T]]], CreateBasicSequenceWire["out", width, NIL, Props[[variableWire, $T]]] ]]; }; latchClass: RoseBind.BehaviorClass = RoseBind.EnsureBehaviorClass["AggerLatch", MakeLatchPW[4]]; DefineLatch: PROC [width: NAT] RETURNS [ct: CellType] = { ct _ NEW [CellTypeRec _ [ public: MakeLatchPW[width], class: unspecifiedCellClass, properties: Props[[nameProp, IO.PutFR["Latch%g", [integer[width]] ]], [classKey, latchClass], [argsKey, NEW [INT _ width]]] ]]; }; MakeCounterPW: PROC [width: NAT] RETURNS [pw: Wire] = { pw _ CreateRecordWire[LIST[ CreateRecordWire[ LIST[CreateAtomWire["phA"], CreateAtomWire["phB"]], "clocks"], CreateRecordWire[ LIST[ CreateBasicSequenceWire["in", width, NIL, Props[[variableWire, $T]]], CreateBasicSequenceWire["out", width, NIL, Props[[variableWire, $T]]] ], "io"], CreateAtomWire["load"] ]]; }; counterClass: RoseBind.BehaviorClass = RoseBind.EnsureBehaviorClass["AggerCounter", MakeCounterPW[4]]; DefineCounter: PROC [width: NAT] RETURNS [ct: CellType] = { ct _ NEW [CellTypeRec _ [ public: MakeCounterPW[width], class: unspecifiedCellClass, properties: Props[[nameProp, IO.PutFR["Counter%g", [integer[width]] ]], [classKey, counterClass], [argsKey, NEW [INT _ width]]] ]]; }; DefineAgger: PROC RETURNS [ct: CellType] = { phA: Wire _ CreateAtomWire["phA"]; phB: Wire _ CreateAtomWire["phB"]; loadCounter: Wire _ CreateAtomWire["loadCounter"]; loadLatches: Wire _ CreateAtomWire["loadLatches"]; in: Wire _ CreateBasicSequenceWire["in", 16]; mid: Wire _ CreateBasicSequenceWire["mid", 16]; out: Wire _ CreateBasicSequenceWire["out", 16]; pw: WireSequence = WiresToWireSequence[LIST[phA, phB, loadCounter, loadLatches, in, out]]; iw: WireSequence = WiresToWireSequence[LIST[phA, phB, loadCounter, loadLatches, in, mid, out]]; counter: CellInstance = NEW [CellInstanceRec _ [ properties: Props[[nameProp, "counter"]], actual: WiresToWireSequence[LIST[ CreateRecordWire[LIST[phA, phB], "clocks"], CreateRecordWire[LIST[in, mid], "io"], loadCounter ]], type: DefineCounter[16] ]]; latchType: CellType = DefineLatch[8]; latch0: CellInstance = NEW [CellInstanceRec _ [ properties: Props[[nameProp, "latch0"]], actual: WiresToWireSequence[LIST[ loadLatches, SubrangeWire[mid, 0, 8], SubrangeWire[out, 0, 8] ]], type: latchType ]]; latch1: CellInstance = NEW [CellInstanceRec _ [ properties: Props[[nameProp, "latch1"]], actual: WiresToWireSequence[LIST[ loadLatches, SubrangeWire[mid, 8, 8], SubrangeWire[out, 8, 8] ]], type: latchType ]]; ct _ NEW [CellTypeRec _ [ properties: Props[[nameProp, "Agger"]], public: pw, class: recordCellClass, data: NEW [RecordCellTypeRec _ [iw, LIST[counter, latch0, latch1]]] ]]; }; CreateBasicSequenceWire: PROC [name: ROPE, length: NAT, eltProps, props: Properties _ NIL] RETURNS [wire: Wire] = { elts: LIST OF Wire _ NIL; FOR i: NAT DECREASING IN [0 .. length) DO elts _ CONS[CreateAtomWire[props: eltProps], elts]; ENDLOOP; wire _ CreateSequenceWire[elts, name, props]; }; SubrangeWire: PROC [wire: Wire, start, length: NAT, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [sub: Wire] = { elts: LIST OF Wire _ NIL; FOR i: NAT DECREASING IN [0 .. length) DO elts _ CONS[wire.elements[start+i], elts]; ENDLOOP; sub _ CreateSequenceWire[elts, name, props]; }; END.  Agger.mesa Copyright c 1985 by Xerox Corporation. All rights reversed. Barth, August 1, 1985 2:31:39 pm PDT Spreitzer, November 18, 1985 10:47:20 pm PST Κ>– "cedar" style˜– "Cedar" stylešœ ™ Jšœ Οmœ1™