<> <> <> <> Core Run -a PortsImpl Run -a RosemaryImpl Run -a SSIImpl <<>> _ &AndVdd _ 0; _ &AndGnd _ 1; _ &AndInput _ 2; _ &AndOutput _ 3; _ &ct _ SSI.And[2] _ Ports.InitTesterDrive[wire: &ct.public[&AndInput][0], initDrive: force] _ Ports.InitTesterDrive[wire: &ct.public[&AndInput][1], initDrive: force] _ Ports.InitTesterDrive[wire: &ct.public[&AndOutput], initDrive: none] _ Rosemary.SetFixedWire[&ct.public[&AndVdd], H] _ Rosemary.SetFixedWire[&ct.public[&AndGnd], L] _ &tp _ Ports.CreatePort[&ct.public, TRUE] -- _ CoreOps.Print[&ct] -- _ &sim _ Rosemary.InstantiateCellType[&ct, &tp] -- _ &sim _ Rosemary.InstantiateInstances[&ct, &tp, "JustAboveTransistors"] _ &sim _ Rosemary.InstantiateInstances[&ct, &tp] _ &tp[&AndInput][0].b _ FALSE _ &tp[&AndInput][1].b _ FALSE _ Rosemary.Settle[&sim, NIL] _ &tp[&AndOutput].b -- FALSE _ Rosemary.WireValue[&sim, [0, ALL[FALSE]], &ct.public[&AndOutput]] -- L _ &tp[&AndInput][0].b _ TRUE _ &tp[&AndInput][1].b _ TRUE _ Rosemary.Settle[&sim, NIL] _ &tp[&AndOutput].b -- TRUE _ Rosemary.WireValue[&sim, [0, ALL[FALSE]], &ct.public[&AndOutput]] -- H _ &tp[&AndInput][0].b _ TRUE _ &tp[&AndInput][1].b _ FALSE _ Rosemary.Settle[&sim, NIL] _ &tp[&AndOutput].b -- FALSE _ Rosemary.WireValue[&sim, [0, ALL[FALSE]], &ct.public[&AndOutput]] -- L _ Rosemary.WireValue[&sim, CoreFlat.ComputePackedPath[&ct, LIST[&ct.data[0]]], &ct.data[0].type.data[0].actual[1]] -- H _ &tp[&AndInput][0].b _ FALSE _ &tp[&AndInput][1].b _ TRUE _ Rosemary.Settle[&sim, NIL] _ &tp[&AndOutput].b -- FALSE _ Rosemary.WireValue[&sim, [0, ALL[FALSE]], &ct.public[&AndOutput]] -- L _ Rosemary.WireValue[&sim, CoreFlat.ComputePackedPath[&ct, LIST[&ct.data[0]]], &ct.data[0].type.data[0].actual[1]] -- L