<> <> <> DIRECTORY Asserting, Basics, Core, CoreClasses, IO, PrincOps, Rope, RedBlackTree, RoseBehavior, RoseBindPrivate, RoseControl, RoseEvents, RosePrivates, RoseWireTypes, VFonts; RoseSimTypes: CEDAR DEFINITIONS = <> BEGIN OPEN RoseWireTypes; CellType: TYPE = Core.CellType; CellInstance: TYPE = CoreClasses.CellInstance; CellInstanceList: TYPE = CoreClasses.CellInstanceList; roseWireTypeKey: ATOM; <> <> roseWireKey: ATOM; <> <> < sim -> RoseWire.>> roseCellKey: ATOM; <> < sim -> RoseCellInstance.>> RoseWireList: TYPE = LIST OF RoseWire; RoseWire: TYPE = REF RoseWireRep; RoseWireRep: TYPE = RECORD [ schIn: Scheduling, core: Wire, type: RoseWireType, valPtr: Ptr _ nilPtr, bitCount: INT _ 0, <> capStrength: Strength _ charge, <> group: WireGroup, <> holdStrength: Strength _ charge, <> forceScope: RoseControl.ForceScope _ notForced, winnerStrength: Strength _ charge, <> switchConnections: SlotList _ NIL, byStrength: ARRAY Strength OF StrengthRingHead _ ALL[emptyHead], found, XPhobic, isInput: BOOLEAN _ FALSE, <> nextPerturbed, nextAffected, nextDelayed, prevDelayed: RoseWire _ NIL--compiler can't handle: notInWireList--, watchers: ARRAY Priority OF WatcherList _ ALL[NIL], <> subWires: RoseWireS _ NIL, <> parent: RoseWire _ NIL, myIndex: NAT _ LAST[NAT], other: Assertions _ NIL]; WireGroup: TYPE = {aboveLeaf, leaf, belowLeaf}; notInWireList: RoseWire; SlotList: TYPE = LIST OF Slot; Slot: TYPE = RECORD [ cell: RoseCellInstance, effectivePortIndex: EffectivePortIndex ]; nilSlot: Slot = [NIL, nilEffectivePortIndex]; ModelSlot: TYPE = RECORD [ cell: RoseCellInstance, portPath: PortPath]; nilModelSlot: ModelSlot = [NIL, NIL]; StrengthRingHead: TYPE = RECORD [first, last: Slot]; emptyHead: StrengthRingHead = [head, head]; head: Slot --don't look:-- = nilSlot; Priority: TYPE = {ordinary, high}; <<"ordinary" is for ordinary mortals, like breakpoints>> <<"high" is for things like the display, which should be updated first>> roseCellInstanceKey: ATOM; <> <> RoseCellType: TYPE = REF RoseCellTypeRep; RoseCellTypeRep: TYPE = RECORD [ core: CellType, behaviorClass: RoseBindPrivate.BehaviorClass, wireTypes: ARRAY WireFlavor OF RoseWireType, other: Assertions _ NIL]; RoseCellInstance: TYPE = REF RoseCellInstanceRep; RoseCellInstanceRep: TYPE = RECORD [ schIn: Scheduling, core: CellInstance, args: REF ANY, type: RoseCellType, effectivePorts: EffectivePortS, connectedWires: RoseWireS, schedNext, nextNeeded, nextNoted: RoseCellInstance _ NIL--notInCellList--, newIO, oldIO, switchIO, newDrive, oldDrive: REF ANY, locked: BOOLEAN _ FALSE, hasTransducedPort: BOOL _ FALSE, affectedFlags: AffectedFlags _ ALL[FALSE], initQed, propQed, initUDed, propUDed: BOOLEAN _ FALSE, state: REF ANY, schedWatchers, evalWatchers: WatcherList _ NIL, other: Assertions _ NIL]; notInCellList: RoseCellInstance; AffectedFlags: TYPE = ARRAY Speciality OF BOOLEAN; Speciality: TYPE = {transducedToSwitch, modeledAsSwitch}; RoseWireS: TYPE = REF RoseWireSeq; RoseWireSeq: TYPE = RECORD [wires: SEQUENCE length: EffectivePortIndex OF RoseWire]; EffectivePortS: TYPE = REF EffectivePortSeq; EffectivePortSeq: TYPE = RECORD [ports: SEQUENCE length: EffectivePortIndex OF EffectivePort]; EffectivePort: TYPE = RECORD [ switch, newSimple, oldSimple, newDrive, oldDrive: Ptr, type: RoseWireType, <> implType: RoseWireType, <> path: PortPath _ NIL, <> strengthNext, strengthPrev: Slot _ nilSlot, curStrength: Drive _ test, <> input, output, XPhobic, transduced: BOOLEAN, other: Assertions _ NIL ]; EffectivePortIndex: TYPE = CARDINAL; nilEffectivePortIndex: EffectivePortIndex = LAST[EffectivePortIndex]; Simulation: TYPE = REF SimulationRec; SimulationRec: TYPE = RECORD [ flatRootType: CellType, rootRecordType: CoreClasses.RecordCellType, sch: Scheduling, other: Assertions _ NIL]; Scheduling: TYPE = REF SchedulingRep; SchedulingRep: TYPE = RECORD [ sim: Simulation, schedFirst, schedLast, firstNeeded: RoseCellInstance _ NIL, firstPerturbed, firstAffected, firstDelayed, lastDelayed: RoseWire _ NIL, running: BOOL _ FALSE ]; CellTestHandle: TYPE = REF CellTestHandleRep; CellTestHandleRep: TYPE = RECORD [ sim: Simulation, expanded: BOOL, testerCT, testeeCT: CellType, testerCI, testeeCI: CellInstance _ NIL, switchInstructions: REF ANY _ NIL, simpleInstructions: REF ANY _ NIL, driveInstructions: REF ANY _ NIL, driveInstructionsAsPtr: Ptr _ nilPtr, testerRCT, testeeRCT: RoseCellType, testerRCI, testeeRCI: RoseCellInstance _ NIL, instructionFields: EffectivePortS _ NIL, <> test: CellTest _ NIL, ctl: TestControl _ NIL ]; TestControl: TYPE = REF TestControlRec; TestControlRec: TYPE = RECORD [stopBefore, stopAfter: BOOL _ FALSE]; CellTest: TYPE = REF CellTestRec; CellTestRec: TYPE = RECORD [ testProc: RoseControl.TestProc, testData: REF ANY _ NIL, stateToo: BOOL _ FALSE ]; END.