DIRECTORY CD, Core, CoreClasses, CoreCreate, CoreOps, PW, PWCore; PWCoreInverter: CEDAR PROGRAM IMPORTS CoreClasses, CoreCreate, CoreOps, PW, PWCore = BEGIN sourceDesign: CD.Design _ PW.OpenDesign["PWCoreInverter"]; CellType: TYPE = Core.CellType; Wire: TYPE = Core.Wire; Foo: PROC [] RETURNS [cellType: CellType] = { pinFoo: Wire _ CoreOps.CreateWire[name: "pinFoo"]; cellType _ CoreClasses.CreateRecordCell[ public: CoreOps.CreateWire[LIST [pinFoo]], internal: CoreOps.CreateWire[LIST [pinFoo]], instances: NIL, name: "Foo" ]; PWCore.SetGet[cellType, sourceDesign]; }; Bar: PROC [] RETURNS [cellType: CellType] = { pinBar: Wire _ CoreOps.CreateWire[name: "pinBar"]; cellType _ CoreClasses.CreateRecordCell[ public: CoreOps.CreateWire[LIST [pinBar]], internal: CoreOps.CreateWire[LIST [pinBar]], instances: NIL, name: "Bar" ]; PWCore.SetGet[cellType, sourceDesign]; }; FooBar: PROC [] RETURNS [cellType: CellType] = { ww: Wire _ CoreOps.CreateWire[name: "ww"]; cellType _ CoreClasses.CreateRecordCell[ public: CoreOps.CreateWire[NIL], internal: CoreOps.CreateWire[LIST [ww]], instances: LIST [ NEW [CoreClasses.CellInstanceRec _ [ actual: CoreOps.CreateWire[LIST [ww]], type: Foo[]]], NEW [CoreClasses.CellInstanceRec _ [ actual: CoreOps.CreateWire[LIST [ww]], type: Bar[]]], ], name: "FooBar" ]; PWCore.SetAbutX[cellType]; }; CreateInverter: PROC [] RETURNS [cellType: CellType] = { In: Wire _ CoreOps.CreateWire[name: "In"]; Out: Wire _ CoreOps.CreateWire[name: "Out"]; Gnd: Wire _ CoreOps.CreateWire[name: "Gnd"]; Vdd: Wire _ CoreOps.CreateWire[name: "Vdd"]; ntrans: CoreClasses.CellInstance _ NEW [CoreClasses.CellInstanceRec _ [ actual: CoreOps.CreateWire[LIST [In, Out, Gnd]], type: CoreClasses.CreateTransistor[[nE]] ]]; ptrans: CoreClasses.CellInstance _ NEW [CoreClasses.CellInstanceRec _ [ actual: CoreOps.CreateWire[LIST [In, Out, Vdd]], type: CoreClasses.CreateTransistor[[pE]] ]]; cellType _ CoreClasses.CreateRecordCell[ public: CoreOps.CreateWire[LIST [In, Out, Gnd, Vdd]], internal: CoreOps.CreateWire[LIST [In, Out, Gnd, Vdd]], instances: LIST [ntrans, ptrans], name: "Inverter" ]; PWCore.SetGet[cellType, sourceDesign]; }; Create2Inverter: PROC [] RETURNS [cellType: CellType] = { In: Wire _ CoreOps.CreateWire[name: "In"]; Out: Wire _ CoreOps.CreateWire[name: "Out"]; Gnd: Wire _ CoreCreate.Seq[size:2, name: "Gnd"]; Vdd: Wire _ CoreCreate.Seq[size:2, name: "Vdd"]; Intern: Wire _ CoreOps.CreateWire[name: "Intern"]; inverter: CellType _ CreateInverter[]; first: CoreClasses.CellInstance _ NEW [CoreClasses.CellInstanceRec _ [ actual: CoreOps.CreateWire[LIST [In, Intern, Gnd[0], Vdd[0]]], type: inverter ]]; second: CoreClasses.CellInstance _ NEW [CoreClasses.CellInstanceRec _ [ actual: CoreOps.CreateWire[LIST [Intern, Out, Gnd[1], Vdd[1]]], type: inverter ]]; cellType _ CoreClasses.CreateRecordCell[ public: CoreOps.CreateWire[LIST [In, Out, Gnd, Vdd]], internal: CoreOps.CreateWire[LIST [In, Out, Gnd, Vdd, Intern]], instances: LIST [first, second], name: "Inverter2" ]; PWCore.SetAbutX[cellType]; }; Layout2Inverter: PW.UserProc = { ob _ PWCore.Layout[Create2Inverter[]]; }; PW.Register[Layout2Inverter, "Layout2Inverter"]; END. όPWCoreInverter.mesa Copyright c 1985 by Xerox Corporation. All rights reversed. Created by Bertrand Serlet, October 15, 1985 8:50:55 am PDT Bertrand Serlet February 6, 1986 6:04:49 pm PST Barth, January 13, 1986 2:35:54 pm PST Basics Small tests Inverters CreateInverters: PROC [n: NAT] RETURNS [cellType: CellType] = { cellType _ CoreSequence.Create[NIL, "ALotOfInverters", NEW [CoreSequence.SequenceCellTypeRec _ [base: CreateInverter[], count: n, ...]]; PWCore.SetArrayX[cellType]; }; Inverters Κα˜codešœ™Kšœ Οmœ1™