LichenDataOps:
CEDAR
DEFINITIONS =
BEGIN OPEN LichenDataStructure, LichenSetTheory;
EnsureAllIn:
PROC [design: Design];
= ct deisgn : EnsurePrivate[ct]
EnsurePublic:
PROC [ct: CellType];
Make sure interface is fully defined.
EnsurePrivate:
PROC [ct: CellType];
Make sure the internals are as known as possible.
ExpansionKnown:
PROC [ct: CellType]
RETURNS [known:
BOOL];
Do we know how this cell type is decomposed?
AssertionOp: TYPE = {ignore, report, check, establish};
MerelyCheckableAssertionOp: TYPE = AssertionOp [ignore .. check];
FailableAssertionOp: TYPE = AssertionOp [report .. check];
CheckDesign: PROC [design: Design, rep, norm: AssertionOp, comparable: MerelyCheckableAssertionOp];
CheckCellType: PROC [ct: CellType, rep, norm: AssertionOp, comparable: MerelyCheckableAssertionOp, interface, internals, instances: BOOL ← TRUE];
CheckCellTypes: PROC [cts: Set--of CellType--, rep, norm: AssertionOp, comparable: MerelyCheckableAssertionOp, interface, internals, instances: BOOL ← TRUE];
NoteChange: PROC [cellType: CellType];
AddPort:
PROC [p: PortPrivate ← []]
RETURNS [port: Port];
Adds as last child of parent, if any.
FullyAddPort:
PROC [p: PortPrivate ← [], andReportConnectionTo: CellInstance ←
NIL]
RETURNS [port: Port, connection: Wire ←
NIL];
Adds dummy wires by instances.
RemovePort: PROC [port: Port];
AddEdge: PROC [vs: ARRAY GraphDirection OF Vertex, port: Port];
AddEdges:
PROC [vs:
ARRAY GraphDirection
OF Vertex, port: Port];
Will introduce Intermediaries, if necessary.
RemoveEdge: PROC [e: Edge];
RemoveEdges:
PROC [e: Edge];
Removes ancestor Intermediaries that have no children.
UnlinkPort:
PROC [ci: CellInstance, port: Port];
Remove the edge for given port.
Instantiate: PROC [type, containingCT: CellType, other: Assertions ← NIL] RETURNS [ci: CellInstance];
CreateWire:
PROC [containingCT: CellType, containingWire: Wire ←
NIL, other: Assertions ←
NIL, copy: Wire ←
NIL]
RETURNS [w: Wire];
As last child of containingWire, if any.
With same structure as copy, if given, leaf structure otherwise.
CreateIntermediary: PROC [from: Vertex, go: GraphDirection, containingCT: CellType, port: Port, other: Assertions ← NIL] RETURNS [im: Intermediary];
KnowVertexName: PROC [v: Vertex, name: ROPE];
DeleteVertex: PROC [v: Vertex];
IsMirror: PROC [v: CellInstance] RETURNS [isMirror: BOOL];
AddMirror: PROC [CellType];
MergeNets: PROC [net1, net2: Wire] RETURNS [merged, doomed: Wire];
MakeArrayConnection: PROC [ct: CellType, d: Dim, lowRange: Range2, lowPort, highPort: Port];
SetArrayPort: PROC [a: Array, index: ArrayIndex, ep, ap: Port];
Log: PROC [fmt: ROPE, v1, v2, v3, v4, v5: REF ANY ← NIL];
END.