CIRCUIT[Lambda ← 1, TDegC ← 25] = {
Vdd: Node;
! /DATools/DATools6.0/Thyme/SignalGenerators.thy
! /DATools/DATools6.0/Thyme/BSim.thy
powerSupply: voltage[Vdd, Gnd] = 5.0;
jn1, jn2, jn3, jn4, jn5, driveGate: Node;
myDriver: CIRCUIT[gate, source, drain] = {
n1, n2: Node;
R10: Resistor[source, n1] = 0.01986K;
C9: Capacitor[n1, Gnd] = 1.0pF;
R5: Inductor[n1, n2] = 1.986nH;
Q1: CTran[gate, n2, drain| L ← 6, W ← 20, sdExtend ← 6];
};
R3: Resistor[jn1, jn2] = 0.01986K;
R4: Resistor[jn2, jn3] = 0.01986K;
R5: Inductor[jn3, jn4] = 19.86nH;
R6: Resistor[jn4, jn5] = 0.01986K;
C0: Capacitor[jn1, Gnd] = 0.1pF;
C1: Capacitor[jn2, Gnd] = 0.1pF;
C2: Capacitor[jn3, Gnd] = 0.1pF;
C3: Capacitor[jn5, Gnd] = 0.1pF;
Qx: ETran[driveGate, jn4, Gnd| L ← 2, W ← 4, sdExtend ← 3];
LineDriver: myDriver[driveGate, Vdd, jn3];
gatePulse: Step[driveGate | OnLevel ← 0V, OffLevel ← 5V, tRise ← 1ns, tDelay ← 2ns];
};