JasmineDoc.tioga
Created by Neil Gunther, January 27, 1986 2:56:07 pm PST
Last Edited by: Neil Gunther June 12, 1986 6:50:32 pm PDT
JASMINE: A STATIC IC NETWORK ANALYZER
JASMINE: A STATIC IC NETWORK ANALYZER
JASMINE: A STATIC IC NETWORK ANALYZER
DATOOLS — FOR INTERNAL XEROX USE ONLY
DATOOLS — FOR INTERNAL XEROX USE ONLY
DATOOLS — FOR INTERNAL XEROX USE ONLY
Jasmine
Neil Gunther
© Copyright 1985 Xerox Corporation. All rights reserved.
Abstract: Static checks that some interesting invariants hold.
Created by: Neil Gunther
Maintained by: Gunther <Gunther.pa>
Keywords: Design automation, Jasmine, LRC network, Inductance, Resistance, Capacitance, Parasitics, Voltage bounce analysis.
XEROX Xerox Corporation
Palo Alto Research Center
3333 Coyote Hill Road
Palo Alto, California 94304
For Internal Xerox Use Only
Some preliminary comments follow.
Purpose
Enumerate the rectangles belonging to a Core wire, and transform them into the equivalent lumped LRC network. Analyze the degree of voltage bounce, taking into account diode thresholds, block circuit transitions, etc., etc..
Manual Static Analysis Procedure
To compute voltage drops in the power bus due to peak current flow the power bus is modeled as a tree that is rooted at the pad and branches at each major block shown on the floor plan. Each node in the tree represents a junction of lower level power buses. Each link in the tree represents the metal required to join one junction to the next. The voltage drop in each link of the tree is the sum of the currents required by each of the leaf blocks beneath the link, multiplied by the resistance of the link.
User Interface
A particular (static) bus analysis is initiated by selecting it from the layout. The user should be able to specify which subcircuits to include or ignore in the analysis & also provide predetermined values/states for the lumped element network. The results of the analysis should be fed back to the user via the original layout for circuit debugging purposes.
Rectangle Preprocessing (April 24, 1986)
All the rectangles on a Core wire need to be enumerated so that compound areas i.e. rectangles composed of several abutting and overlapping rectangles of arbitrary size, can be detected and treated as special cases before the transformation to the equivalent circuit. Moreover, the fissioning algorithm described below depends on a knowledge of the orientation of the length and width dimensions of the intersecting rectangles. Since the code is readily available, it is proposed to preprocess the Core wire into a Canonical form using a Corner Stitching data structure.
Fission Tree (April 23, 1986)
Think of a simple network of rectangles where all rectangle intersections form only T junctions. Then a rectangle, with its attendent data, is represented as a node in a binary tree. Let a particular rectangle instance be the parent node. When a new rectangle (child) is discovered to intersect this parent, it causes the parent rectangle to fission into two pieces (i.e., either side of the crossbar on the T). The intersecting rectangle is therefore inserted into the tree according to the following recursive algorithm. Each of the two intersected rectangles at the T junction have their geometries recomputed to reflect the fact that they have been fissioned and the intersecting rectangle is recomputed to account for overlaps. The parent node, which has become one of the fission products, has its data updated while the other fissioned rectangle is inserted as a node below the parent, to the left, while the intersecting rectangle is inserted as a node below and to the right. The next intersecting rectangle is matched against already fissioned rectangles (using their original dimensions) in the tree and the recursive process continues. Generalizing this approach to include 4-way intersections, and compound areas requires going to an n-ary tree.