<> <> <> <> <> <> DIRECTORY Rope; IMSTester: CEDAR DEFINITIONS = BEGIN <> <> <> <> ROPE: TYPE = Rope.ROPE; Delay: TYPE = [0..31000); --valid in 1nS increments Width: TYPE = [20..31000); --valid in 10nS increments Sample: TYPE = [0..31000); --valid in 1nS increments Period: TYPE = [50..40000); --valid in 10nS increments ForceGroups: TYPE = LIST OF ForceGroup; ForceGroup: TYPE = REF ForceGroupRec; ForceGroupRec: TYPE = RECORD [ name: ROPE, podTimingGroups: PodTimingGroups, format: FormatType, delay: Delay, -- only if format is not NRZ, 0nS to 30.99uS, 1nS increments width: Width, -- only if format is not NRZ or DNRZ, 20nS to 30.99uS, 10nS increments programable: BOOL, -- indicates programable driver group hiDrive: REAL, -- only if programable driver, +/-5 volt range, 10mV increments loDrive: REAL]; -- only if programable driver, +/-5 volt range, 10mV increments FormatType: TYPE = {NRZ, DNRZ, RZ, R1, RC, RI}; AcquireGroups: TYPE = LIST OF AcquireGroup; AcquireGroup: TYPE = REF AcquireGroupRec; AcquireGroupRec: TYPE = RECORD [ name: ROPE, podTimingGroups: PodTimingGroups, sample: Sample, -- 0nS to 30.99uS, 1nS increments compare: BOOL, -- must have an adjacent pattern generator module programable: BOOL, -- indicates programable receiver group threshold: REAL]; -- only if programable receiver, +/-5 volt range, 10mV increments PodTimingGroups: TYPE = LIST OF PodTimingGroup; PodTimingGroup: TYPE = REF PodTimingGroupRec; PodTimingGroupRec: TYPE = RECORD [ slot: SlotNumber, board: Board, podTiming: PodTiming, pins: Pins]; SlotNumber: TYPE = [1..24]; -- Each module slot in the IMS mainframe is numbered 1 through 12, starting with the master and continuing up to a maximum of three slaves. Board: TYPE = [0..14); -- Current number of purchased Force/Acquire board pairs. PodTiming: TYPE = {A, B, AT, BT}; -- AT, BT must be RZ or R1 Pins: TYPE = LIST OF Pin; Pin: TYPE = REF PinRec; PinRec: TYPE = RECORD[ channel: Channel, --ignored if AT or BT signalName: ROPE, packagePin: NAT]; Channel: TYPE = [0..8); Buffer: TYPE = REF BufferRec; BufferRec: TYPE = RECORD[cycles: SEQUENCE cycle: Cycle OF CycleData]; Cycle: TYPE = [0..16*1024); CycleData: TYPE = REF CycleDataRec; CycleDataRec: TYPE = RECORD[eachCycle: ARRAY Board OF PACKED ARRAY PodChannel OF Data]; PodChannel: TYPE = [0..18); -- 0..7 = A0-A7, 8..15 = B0-B7, 16 = AT, 17 = BT Data: TYPE = RECORD[ forceData: BOOL, inhibit: BOOL, compareData: BOOL, mask: BOOL]; Jumps: TYPE = LIST OF Jump; Jump: TYPE = RECORD [ source: Cycle, destination: Cycle]; Errors: TYPE = LIST OF Error; Error: TYPE = RECORD [ cycle: Cycle, group: AcquireGroup, podTimingGroup: PodTimingGroup, pin: Pin, expected: BOOL, acquired: BOOL]; <> stop: BOOL; <> checkSyntax: BOOL; <> <> IMSError: SIGNAL [msg: ROPE]; RunDiagnostics: PROC [extended: BOOL _ TRUE]; <> Initialize: PROC RETURNS [forceBoard, acquireBoard, programable: PACKED ARRAY SlotNumber OF BOOLEAN]; <> DefineGroups: PROC [forceGroups: ForceGroups _ NIL, acquireGroups: AcquireGroups _ NIL]; <> RedefineGroups: PROC [forceGroups: ForceGroups _ NIL, acquireGroups: AcquireGroups _ NIL]; <> SetCyclePeriod: PROC [period: Period]; SetIMSMemory: PROC [forceGroups: ForceGroups, acquireGroups: AcquireGroups, buffer: Buffer, cycles: Cycle, halt: Cycle, jumps: Jumps _ NIL]; <> ErrorCount: PROC [] RETURNS [count: LONG CARDINAL]; <> <<>> GetErrors: PROC [acquireGroups: AcquireGroups, buffer: Buffer, maxErrors: NAT, startCycle: Cycle, lastCycle: Cycle] RETURNS [errors: Errors]; <> Start: PROC; Stop: PROC; Wait: PROC; -- waits for HALT instruction to be executed END.