DIRECTORY Basics, Commander, Core, CoreOps, IO, ICTest, Ports, Rope, TerminalIO, TestCable; TestCableImpl: CEDAR PROGRAM IMPORTS Basics, IO, CoreOps, Ports, Rope, TerminalIO EXPORTS TestCable = BEGIN groups: PUBLIC LIST OF ICTest.Group; assignments: PUBLIC LIST OF ICTest.Assignments; public: PUBLIC Core.Wire; TestCable: PUBLIC ICTest.TestProc = { EachPair: PROC [wire: Core.Wire, port: Ports.Port] RETURNS [subElements: BOOL _ TRUE, quit: BOOL _ FALSE] --Ports.EachPortPairProc-- = { Cycle: PROC = { Eval[force]; Eval[sense]; }; IF port#NIL THEN port.d _ force; IF CoreOps.IsFullWireName[public, wire, a.name] AND a.group#0 THEN { IF port=NIL THEN SELECT rootPort.type FROM ls => {}; bs => {}; c => {rootPort.c _ Basics.BITSHIFT[08000h, -rootPort.fieldStart-count]; Cycle[]; rootPort.c _ 0; Cycle[]}; lc => {rootPort.lc _ Basics.DoubleShift[[lc[080000000h]], -rootPort.fieldStart-count].lc; Cycle[]; rootPort.lc _ 0; Cycle[]}; ENDCASE => ERROR ELSE SELECT port.type FROM l => {port.l _ L; Cycle[]; port.l _ H; Cycle[]}; b => {port.b _ TRUE; Cycle[]; port.b _ FALSE; Cycle[]}; ENDCASE => ERROR } ELSE IF port#NIL THEN SELECT port.type FROM l => port.l _ L; ls => {}; b => port.b _ FALSE; bs => {}; c => port.c _ 0; lc => port.lc _ 0; ENDCASE; IF port#NIL AND port.type#composite THEN {count _ 0; rootPort _ port} ELSE count _ count+1; }; directionality: ICTest.Directionality _ force; probe: INT _ 1; count: NAT _ 0; lastPin: NAT _ 0; a: ICTest.Assignments; rootPort: Ports.Port; TerminalIO.WriteRope["\n\nProbe Card Tester\n"]; FOR l: LIST OF ICTest.Assignments _ assignments, l.rest WHILE l#NIL DO lastPin _ MAX[l.first.probeCardPin, lastPin]; ENDLOOP; WHILE probe <= lastPin DO FOR l: LIST OF ICTest.Assignments _ assignments, l.rest WHILE l#NIL DO a _ l.first; IF a.probeCardPin = probe THEN { FOR l: LIST OF ICTest.Group _ groups, l.rest WHILE l#NIL DO IF l.first.number=a.group THEN { directionality _ l.first.directionality; EXIT; } ENDLOOP; SELECT TRUE FROM directionality=acquire => { TerminalIO.WriteRope[IO.PutFR["Pin %g is acquire only\n", IO.int[probe]]]; probe _ probe+1; directionality _ force; }; Rope.Equal[s1: a.name, s2: "vdd", case: FALSE] => { TerminalIO.WriteRope[IO.PutFR["Pin %g is Vdd\n", IO.int[probe]]]; probe _ probe+1; }; Rope.Equal[s1: a.name, s2: "gnd", case: FALSE] => { TerminalIO.WriteRope[IO.PutFR["Pin %g is Gnd\n", IO.int[probe]]]; probe _ probe+1; }; a.group=0 => { TerminalIO.WriteRope[IO.PutFR["Pin %g is unused, %g\n", IO.int[probe], IO.rope[a.name]]]; probe _ probe+1; }; ENDCASE => { TerminalIO.WriteRope[IO.PutFR["Ready to test pin %g, %g ...", IO.int[probe], IO.rope[a.name]]]; SELECT TerminalIO.RequestChar[""] FROM 'b, 'B => { probe _ probe-1; TerminalIO.WriteRope["\n"]; }; 'j, 'J => { --jump probe _ TerminalIO.RequestInt["\nJump to pin: "]; IF probe < 1 THEN probe _ 1; IF probe >LAST[ICTest.ProbeCardPin] THEN probe _ LAST[ICTest.ProbeCardPin]; LOOP; }; 'q, 'Q => GOTO quit; 'r, 'R => probe _ probe; --redo ENDCASE => { probe _ probe+1; }; [] _ Ports.VisitBinding[public, p, EachPair]; TerminalIO.WriteRope["done\n"]; }; EXIT; }; REPEAT FINISHED => { TerminalIO.WriteRope[IO.PutFR["Pin %g not found\n", IO.int[probe]]]; probe _ probe+1; }; ENDLOOP; ENDLOOP; EXITS quit => {}; }; END. ŽTestCableImpl.mesa Copyright c 1986 by Xerox Corporation. All rights reserved. Last Edited by: Gasbarro April 18, 1986 9:35:11 am PST Êɘ™Icodešœ Ïmœ1™