DIRECTORY Core; Ports: CEDAR DEFINITIONS = BEGIN Port: TYPE = REF PortRec; PortRec: TYPE = RECORD [ type: PortType _ composite, d: Drive _ none, l: Level _ L, ls: LevelSequence _ NIL, b: BOOL _ FALSE, bs: BoolSequence _ NIL, fieldStart: [0..32) _ 0, c: CARDINAL _ 0, lc: LONG CARDINAL _ 0, composite: SEQUENCE size: NAT OF Port]; PortType: TYPE = {l, ls, b, bs, c, lc, composite}; Drive: TYPE = { expect, -- allows port to specify expected value none, --from a test proc it means neither driven nor checked; in switch-level it means no strength at all chargeWeak, chargeMediumWeak, charge, chargeMediumStrong, chargeStrong, force, -- weakest drive level, allows test procs to check if device has tristated driveWeak, driveMediumWeak, drive, driveMediumStrong, driveStrong, infinite -- drive for nodes which have infinite current sources }; Level: TYPE = {L, H, X}; LevelSequence: TYPE = REF LevelSequenceRec; LevelSequenceRec: TYPE = RECORD [levels: PACKED SEQUENCE size: NAT OF Level]; BoolSequence: TYPE = REF BoolSequenceRec; BoolSequenceRec: TYPE = RECORD [bools: PACKED SEQUENCE size: NAT OF BOOL]; PortList: TYPE = LIST OF Port; CreatePort: PROC [wire: Core.Wire] RETURNS [port: Port]; InitPort: PROC [wire: Core.Wire, initType: PortType _ b, initDrive: Drive _ none]; WirePortType: PROC [wire: Core.Wire] RETURNS [type: PortType]; PortLeaves: PROC [port: Port] RETURNS [leaves: CARDINAL]; PrintPort: PROC [wire: Core.Wire, port: Port, out: Core.STREAM]; CopyPortValue: PROC [from: Port, to: Port]; CheckPortValue: PROC [truth: Port, question: Port]; CheckError: SIGNAL; EachPortPairProc: TYPE = PROC [onePort: Port, anotherPort: Port] RETURNS [subElements: BOOL _ TRUE, quit: BOOL _ FALSE]; VisitPortPair: PROC [onePort: Port, anotherPort: Port, eachPortPair: EachPortPairProc] RETURNS [quit: BOOL]; EachWirePortPairProc: TYPE = PROC [wire: Core.Wire, port: Port] RETURNS [subElements: BOOL _ TRUE, quit: BOOL _ FALSE]; VisitBinding: PROC [wire: Core.Wire, port: Port, eachWirePortPair: EachWirePortPairProc] RETURNS [quit: BOOL]; END. xPorts.mesa Barth, December 20, 1985 7:30:43 pm PST Last Edited by: Gasbarro December 19, 1985 5:54:26 pm PST Theory A port is a DAG which is a subgraph of a Core.Wire DAG. A port requires that the leaves of the port DAG form a disjoint cover of the leaves of the Core.Wire DAG. This eliminates aliases of values. A port is used for representing an interface to a Core.wire. A port defines an interface to a wire rather than the wire itself. Thus a port represents a current strength as well as a voltage level. A voltage level in a port can be represented as a boolean value or as a member of the set L, H, or X. A leaf port can represent aggregates of either of these value sets. A current strength is only represented once for any leaf port. This means that a leaf port which represents an interface to an aggregate of many wires can specify multiple voltage levels but only a single current strength. Types The comment definition of a port record captures the semantics. However it introduces a number of runtime checks and excess verbiage in the source. The uncommented definition is used to eliminate them. PortRec: TYPE = RECORD [ port: SELECT type: PortType FROM l => [d: Drive _ none, l: Level _ L], ls => [d: Drive _ none, ls: LevelSequence _ NIL], b => [d: Drive _ none, b: BOOL _ FALSE], bs => [d: Drive _ none, bs: BitSequence _ NIL], c => [d: Drive _ none, fieldStart: [0..16), c: CARDINAL _ 0], lc => [d: Drive _ none, fieldStart: [0..32), lc: LONG CARDINAL _ 0], composite => [composite: SEQUENCE size: NAT OF Port], ENDCASE]; Operations Prints the port using information found on the wire. Raises an error if the ports are not isomorphic. Raises an error if the ports are not isomorphic or the question port does not match the requirements of the truth port. Enumerating Pairs TRUE is returned if some invocation of eachPortPair returns quit=TRUE or if the ports do not conform. TRUE is returned if some invocation of eachWirePortPair returns quit=TRUE. Wire and port need not conform, but port must be a subgraph of wire. If the port is a strict subgraph of the wire then the EachWirePortPairProc will be called with port: NIL; Êã˜™ J™'Icode™9—J™šÏk œ˜J˜—JšÏnœœœ˜ head™IbodyšœÆ™ÆM™ÇM™‹—™Kšœœœ ˜J™™ËJ™šœ œœ™šœœ™ Kšœ%™%Kšœ,œ™1Kšœœœ™(Kšœ*œ™/Kšœ/œ™=Kšœ1œœ™DKšœœœœ™5Kšœ™ —K™—šœ œœ˜Kšœ˜Kšœ˜K˜ Kšœœ˜Kšœœœ˜Kšœœ˜K˜Kšœœ˜Kšœœœ˜Kšœœœœ˜'K˜——šœ œ$˜2K˜—šœœ˜KšœÏc)˜0šœŸd˜iKšœ˜—šœ˜Kšœ!˜!—šœŸK˜QKšœ˜—šœ˜Kšœ˜—Kšœ Ÿ6˜?Kšœ˜K˜—šœœ ˜K˜—Kšœœœ˜+š œœœ œœœœ˜MK˜—Kšœœœ˜)šœœœ œœœœœ˜JK˜—Kšœ œœœ˜J˜—™ šž œœœ˜8K™—šžœœD˜RK˜—šžœœœ˜>K˜—šž œœœ œ˜9K˜—šž œœ)œ˜@K™4K˜—šž œœ˜+K™0K˜—šžœœ˜3K™wK™Kšž œœ˜K˜——™šžœœœ$œœœœœ˜xJ˜—Kšž œœDœœ˜lšœ=œ ™eK˜—Jšžœœœœœœœœ˜wJ˜šžœœGœœ˜nKšœAœ®œ™ûK˜——Jšœ˜—…—i