DIRECTORY Core, CoreClasses, CoreOps, ICTest, IO, Rope, Ports; EUTest: CEDAR PROGRAM IMPORTS CoreClasses, CoreOps, ICTest, IO, Rope, Ports = BEGIN DC: PROC [n: ICTest.ROPE, s: NAT _ 0, b: ICTest.Board, p: ICTest.PodTiming, c: ICTest.Channel _ 0, d: Ports.Drive] RETURNS [wire: Core.Wire] = { IF s=0 THEN { ICTest.DefineChannel[atomicWire: (wire _ CoreOps.CreateWire[name: n]), board: b, podTiming: p, channel: c]; } ELSE { wireList: LIST OF Core.Wire _ NIL; FOR w: NAT IN [0..s) DO subWire: Core.Wire; name: Rope.ROPE _ Rope.Concat[n, IO.PutFR["%g", IO.int[w]]]; subWire _ CoreOps.CreateWire[name: name]; wireList _ CONS[subWire, wireList]; ICTest.DefineChannel[atomicWire: subWire, board: b, podTiming: p, channel: c]; IF w=s-1 THEN EXIT; [b, p, c] _ ICTest.NextChannel[b, p, c]; ENDLOOP; wire _ CoreOps.CreateWire[name: n, elements: wireList]; }; Ports.InitPort[wire: wire, initType: IF s=0 THEN b ELSE IF s<17 THEN c ELSE lc, initDrive: d]; }; DG: PROC [elements: LIST OF Core.Wire, name: ICTest.ROPE _ NIL, format: ICTest.FormatType, delay: ICTest.NSec _ 0, width: ICTest.NSec _ 0, hiDrive: REAL _ 2.4, loDrive: REAL _ 0.4, sample: ICTest.NSec _ 0, threshold: REAL _ 1.4] RETURNS [wire: Core.Wire] = { wire _ CoreOps.CreateWire[name: name, elements: elements]; ICTest.DefineGroup[wire: wire, groupName: name, format: format, delay: delay, width: width, hiDrive: hiDrive, loDrive: loDrive, sample: sample, threshold: threshold]; }; DW: PROC [name: ICTest.ROPE, d: Ports.Drive] RETURNS [wire: Core.Wire] = { wire _ CoreOps.CreateWire[name: name]; Ports.InitPort[wire: wire, initType: b, initDrive: d]; }; MakeEUCell: PROC [] RETURNS [rootCell: Core.CellType] = { rootCell _ CoreOps.CreateCellType[ class: CoreClasses.unspecifiedCellClass, data: NIL, name: "EU", public: CoreOps.CreateWire[name: "EUPads", elements: LIST[ DG[name: "Clocks", format: RC, delay: 10, width: 30, elements: LIST[ DC[n: "PhA", b: 0, p: A, c: 0, d: none], DC[n: "nPhA", b: 0, p: A, c: 1, d: none], DC[n: "PhB", b: 0, p: A, c: 2, d: none], DC[n: "nPhB", b: 0, p: A, c: 3, d: none]]], CoreOps.CreateWire[name: "Power", elements: LIST[ DW[name: "Vdd", d: none], DW[name: "Gnd", d: none], DW[name: "PadVdd", d: none], DW[name: "PadGnd", d: none]]], DG[name: "MemInterface", format: NRZ, elements: LIST[ DC[n: "MHold", b: 0, p: B, c: 0, d: none], DC[n: "MnReset", b: 0, p: B, c: 1, d: none]]], DG[name: "DebugInterface", format: NRZ, elements: LIST[ DC[n: "DShift", b: 0, p: B, c: 2, d: none], DC[n: "DExecute", b: 0, p: B, c: 3, d: none], DC[n: "DNSelect", b: 0, p: B, c: 4, d: none], DC[n: "DDataIn", b: 0, p: B, c: 5, d: none], DC[n: "DDataOut", b: 0, p: B, c: 6, d: none]]], DG[name: "PInterface", format: NRZ, elements: LIST[ DC[n: "EPParityB", b: 3, p: A, c: 0, d: force], DC[n: "EPRejectB", b: 3, p: A, c: 1, d: force], DC[n: "EPFaultB", s: 3, b: 3, p: A, c: 2, d: force], --Dragon.PBusFaults DC[n: "EPNPErrorB", b: 3, p: A, c: 5, d: force], DC[n: "EPData", s: 32, b: 1, p: A, c: 0, d: force]]], DG[name: "IInterface", format: NRZ, elements: LIST[ DC[n: "EUAluLeftSrc1BA", s: 2, b: 6, p: A, c: 0, d: force],--Dragon.ALULeftSources DC[n: "EUAluRightSrc1BA", s: 3, b: 6, p: A, c: 2, d: force], --Dragon.ALURightSources DC[n: "EUStore2ASrc1BA", s: 2, b: 6, p: A, c: 5, d: force], --Dragon.Store2ASources DC[n: "EUAluOp2AB", s: 4, b: 6, p: B, c: 0, d: force], --Dragon.ALUOps DC[n: "EUCondSel2AB", s: 4, b: 6, p: B, c: 4, d: force], --Dragon.CondSelects DC[n: "EURes3AisCBus2BA", b: 3, p: B, c: 0, d: force], DC[n: "EUSt3AisCBus2BA", b: 3, p: B, c: 1, d: force], DC[n: "EUCondition2BA", b: 3, p: B, c: 2, d: force], DC[n: "EURes3BisPBus3AB", b: 3, p: B, c: 3, d: force], DC[n: "EUCheckParity3AB", b: 3, p: B, c: 4, d: force], DC[n: "EULoadField3BA", b: 3, p: B, c: 5, d: force], DC[n: "EUWriteToPBus3AB", b: 3, p: B, c: 6, d: force], DC[n: "KBus", s: 32, b: 4, p: A, c: 0, d: force]]]]]]; }; EUTestButtons: ICTest.TestButtonsCreateProc = { createButton[buttonName: "Simple", proc: EUSimpleTest]; }; Clocks: NAT = 0; Power: NAT = 1; MemoryInterface: NAT = 2; DebugInterface: NAT = 3; PInterface: NAT = 4; EPParityB: NAT = 0; EPRejectB: NAT = 1; EPFaultB: NAT = 2; EPNPErrorB: NAT = 3; EPData: NAT = 4; IInterface: NAT = 5; EUAluL: NAT = 0; --2 bits EUAluR: NAT = 1; --3 bits EUSimpleTest: ICTest.TestProc = { p[PInterface][EPParityB].b _ TRUE; p[PInterface][EPRejectB].b _ TRUE; p[PInterface][EPFaultB].c _ 7H; p[PInterface][EPNPErrorB].b _ TRUE; p[PInterface][EPData].lc _ 0FFFFFFFFH; p[IInterface][EUAluL].c _ 3H; p[IInterface][EUAluR].c _ 7H; Eval[force]; p[PInterface][EPData].lc _ 0; Eval[force]; p[PInterface][EPParityB].b _ FALSE; p[PInterface][EPRejectB].b _ FALSE; p[PInterface][EPFaultB].c _ 0H; p[PInterface][EPNPErrorB].b _ FALSE; p[PInterface][EPData].lc _ 0FFFFFFFFH; p[IInterface][EUAluL].c _ 0H; p[IInterface][EUAluR].c _ 0H; Eval[force]; }; ICTest.MakeStandardViewer[testButtons: EUTestButtons, cellType: MakeEUCell[], name: "EU Tester"]; END. NEUTest.mesa Copyright c 1985 by Xerox Corporation. All rights reserved. Created by: Gasbarro November 20, 1985 11:35:38 am PST Last Edited by: Gasbarro January 16, 1986 10:16:11 am PST -- board 0, pod A, channels [0..3] -- board 0, pod B, channels [0..1] -- board 0, pod B, channels [2..6] -- board 3, pod A, channels [0..5] -- board 1, pods A&B, channels [0..7] -- board 2, pods A&B, channels [0..7] -- board 6, pod A, channels [0..6] -- board 6, pod B, channels [0..6] -- board 3, pod B, channels [0..6] -- board 4, pods A&B, channels [0..7] -- board 5, pods A&B, channels [0..7] ‌ت_ک™Icodeڑœ دmœ1™