DIRECTORYFS, ICTest, IO, PodToTesterConfigPin, ProbePinToDUTConfigPin, Rope, TestCable, TiogaAccess;ConfiguratorWires: CEDAR PROGRAMIMPORTS FS, IO, PodToTesterConfigPin, ProbePinToDUTConfigPin, Rope, TestCable, TiogaAccess~ BEGINROPE: TYPE = Rope.ROPE;nameFieldWidth: INT _ 26;Main: PROC [fName: ROPE] ~ {out: IO.STREAM _ FS.StreamOpen[Rope.Concat[fName], $create];c: TiogaAccess.TiogaChar;writer: TiogaAccess.Writer;reader: TiogaAccess.Reader;IO.PutF[out, "\n"];IO.PutF[out, "                               L                   \n"];IO.PutF[out, "                               o                   \n"];IO.PutF[out, "                               a          T        \n"];IO.PutF[out, "                               d          e        \n"];IO.PutF[out, "                                          s        \n"];IO.PutF[out, "                               B          t   D    \n"];IO.PutF[out, "                               o          e   U    \n"];IO.PutF[out, "                               a P        r   T    \n"];IO.PutF[out, "                               r o     C          D\n"];IO.PutF[out, "                               d d     h  H   H   U\n"];IO.PutF[out, "                          G  B         a  e   e   T\n"];IO.PutF[out, "                          r  o S P   B n  a   a    \n"];IO.PutF[out, "                          o  a i a   y n  d   d   P\n"];IO.PutF[out, "                          u  r d i   t e  e   e   i\n"];IO.PutF[out, "Signal Name               p  d e r   e l  r   r   n\n"];IO.PutF[out, "---------------------------------------------------\n"];FOR l: LIST OF ICTest.Assignments _ TestCable.assignments, l.rest WHILE l#NIL DOa: ICTest.Assignments _ l.first;IO.PutF[out, a.name];THROUGH [0..nameFieldWidth-Rope.Length[a.name]) DOIO.PutF[out, " "];ENDLOOP;IO.PutF[out, "%g,", IO.int[a.group]];IO.PutF[out, "%2g,", IO.int[a.board]];IO.PutF[out, SELECT a.loadBoardSide FROM L=>"L,", R=>"R,", ENDCASE => ERROR];IO.PutF[out, SELECT a.podPair FROM AB=>"AB,", CD=>"CD,", EF=>"EF,", GH=>"GH,", IJ=>"IJ,", KL=>"KL,", ENDCASE => ERROR];IO.PutF[out, SELECT a.pod FROM A=>" A,", B=>" B,", AT=>"AT,", BT=>"BT,", ENDCASE => ERROR];IO.PutF[out, "%g,", IO.int[a.channel]];IO.PutF[out, "%3g,", IO.int[PodToTesterConfigPin.Map[a.loadBoardSide, a.podPair, (SELECT a.pod FROM A=>0, B=>8, AT=>16, BT=>17 ENDCASE=>ERROR)+a.channel]]];IO.PutF[out, "%3g,", IO.int[ProbePinToDUTConfigPin.Map[a.probeCardPin]]];IO.PutF[out, "%3g\n", IO.int[a.probeCardPin]];ENDLOOP;IO.Close[out];reader _ TiogaAccess.FromFile[fName];writer _ TiogaAccess.Create[];UNTIL TiogaAccess.EndOf[reader] DOc _ TiogaAccess.Get[reader];c.looks['f] _ TRUE;TiogaAccess.Put[writer, c];ENDLOOP;TiogaAccess.WriteFile[writer, fName];TiogaAccess.DoneWith[reader];};END.    Ž  ConfiguratorWires.mesaCopyright c 1986 by Xerox Corporation.  All rights reserved.Last Edited by: Gasbarro May 8, 1986 2:42:04 pm PDTÊð  ˜ ™Icodešœ
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