<> <> <> DIRECTORY Core, CoreCreate, ICTest, Ports, TestCable; Test74LS163: CEDAR PROGRAM IMPORTS CoreCreate, ICTest, Ports, TestCable = BEGIN Nibble: TYPE = [0..16); nClear: NAT = 0; Clock: NAT = 1; DataIn: NAT = 2; --4 bits EnableP: NAT = 3; Gnd: NAT = 4; nLoad: NAT = 5; EnableT: NAT = 6; DataOut: NAT = 7; --4 bits RippleCarryOut: NAT = 8; Vcc: NAT = 9; width: NAT = 4; Init: PROC = { R: PROC [a: ICTest.Assignments] = { TestCable.assignments_CONS[a,TestCable.assignments]; }; ct: Core.CellType _ CoreCreate.Cell[ name: "74LS163", public: CoreCreate.WireList[LIST[ "nClear", "Clock", CoreCreate.Seq["DataIn", width], "EnableP", "Gnd", "nLoad", "EnableT", CoreCreate.Seq["DataOut", width], "RippleCarryOut", "Vcc"]], onlyInternal: NIL, instances: NIL ]; TestCable.groups _ LIST[ [number: 1, name: "DUTInputs", directionality: force, format: DNRZ, delay: 10], [number: 2, name: "DUTOutputs", directionality: acquire, sample: 40], [number: 3, name: "Clocks", directionality: force, format: RZ, delay: 0, width: 20] ]; TestCable.assignments _ NIL; << L>> << o >> << a T>> << d e>> << s>> << B t D>> << o e U>> << a P r T>> << r o C D>> << d d h H H U>> << G B a e e T>> << r o S P B n a a >> << o a i a y n d d P>> << u r d i t e e e i>> <> R[["Gnd", 0,0,R,AB, A,0,001,001, 8]]; R[["Vdd", 0,0,R,AB, A,0,001,001, 16]]; R[["nClear", 1,0,R,AB, A,0,001,001, 1]]; R[["DataIn[0]", 1,0,R,AB, A,1,001,001, 6]]; --MSB R[["DataIn[1]", 1,0,R,AB, A,2,001,001, 5]]; R[["DataIn[2]", 1,0,R,AB, A,3,001,001, 4]]; R[["DataIn[3]", 1,0,R,AB, A,4,001,001, 3]]; --LSB R[["EnableP", 1,0,R,AB, A,5,001,001, 7]]; R[["nLoad", 1,0,R,AB, A,6,001,001, 9]]; R[["EnableT", 1,0,R,AB, A,7,001,001, 10]]; R[["RippleCarryOut", 2,0,R,CD, A,0,001,001, 15]]; R[["DataOut[0]", 2,0,R,CD, A,1,001,001, 14]]; --MSB R[["DataOut[1]", 2,0,R,CD, A,2,001,001, 13]]; R[["DataOut[2]", 2,0,R,CD, A,3,001,001, 12]]; R[["DataOut[3]", 2,0,R,CD, A,4,001,001, 11]]; --LSB R[["Clock", 3,0,R,AB,AT,0,001,001, 2]]; [] _ Ports.InitPort[ct.public[DataIn], c]; [] _ Ports.InitPort[ct.public[DataOut], c]; Ports.InitTesterDrive[ct.public[nClear], force]; Ports.InitTesterDrive[ct.public[Clock], force]; Ports.InitTesterDrive[ct.public[DataIn], force]; Ports.InitTesterDrive[ct.public[EnableP], force]; Ports.InitTesterDrive[ct.public[nLoad], force]; Ports.InitTesterDrive[ct.public[EnableT], force]; Ports.InitTesterDrive[ct.public[DataOut], none]; Ports.InitTesterDrive[ct.public[RippleCarryOut], none]; TestCable.public _ ct.public; ICTest.MakeStandardViewer[name: "74LS163 Tester", cellType: ct, testButtons: LIST[["DoTest", DoTest], ["TestCable", TestCable.TestCable]], groups: TestCable.groups, assignments: TestCable.assignments, period: 60]; }; DoTest: ICTest.TestProc = { count: Nibble; temp: Nibble; Cycle: PROC = { t: Nibble _ p[DataOut].c; p[DataOut].c _ temp; p[RippleCarryOut].b _ temp=15; temp _ t; Eval[force]; Eval[sense] }; InitState: PROC ~ { p[nClear].b _ FALSE; p[Clock].b _ TRUE; --fire clock pulse every cycle p[DataIn].c _ 0; p[EnableP].b _ TRUE; p[nLoad].b _ TRUE; p[EnableT].b _ TRUE; p[DataOut].d _ none; p[RippleCarryOut].d _ none; p[DataOut].c _ 0; count _ 0; Cycle[]; p[DataOut].d _ expect; p[RippleCarryOut].d _ expect; }; Clear: PROC ~ { p[nClear].b _ FALSE; p[DataOut].c _ 0; count _ 0; p[RippleCarryOut].b _ FALSE; Cycle[]; p[nClear].b _ TRUE; }; Load: PROC [value: Nibble] ~ { p[nLoad].b _ FALSE; p[DataIn].c _ value; p[DataOut].c _ value; count _ value; p[RippleCarryOut].b _ count=15; Cycle[]; p[nLoad].b _ TRUE; }; IncCount: PROC ~ { count _ IF count=15 THEN 0 ELSE count+1; }; Count: PROC ~ { IncCount[]; p[DataOut].c _ count; p[RippleCarryOut].b _ count=15; Cycle[]; }; InitState[]; Clear[]; THROUGH [0..16) DO Count[]; ENDLOOP; <> <> <> <> <> }; Init[]; END.