<> <> <> <<>> DIRECTORY Core; Ports: CEDAR DEFINITIONS = BEGIN <> <> <> <> <> Port: TYPE = REF PortRec; <<>> <> <<>> <> <> < [d: Drive _ none, l: Level _ L],>> < [d: Drive _ none, ls: LevelSequence _ NIL],>> < [d: Drive _ none, b: BOOL _ FALSE],>> < [d: Drive _ none, bs: BitSequence _ NIL],>> < [d: Drive _ none, fieldStart: [0..16), c: CARDINAL _ 0],>> < [d: Drive _ none, fieldStart: [0..32), lc: LONG CARDINAL _ 0],>> < [composite: SEQUENCE size: NAT OF Port],>> <> <<>> PortRec: TYPE = RECORD [ type: PortType _ composite, d: Drive _ none, l: Level _ L, ls: LevelSequence _ NIL, b: BOOL _ FALSE, bs: BoolSequence _ NIL, fieldStart: [0..32) _ 0, c: CARDINAL _ 0, lc: LONG CARDINAL _ 0, composite: SEQUENCE size: NAT OF Port]; PortType: TYPE = {l, ls, b, bs, c, lc, composite}; Drive: TYPE = { expect, -- allows port to specify expected value none, --from a test proc it means neither driven nor checked; in switch-level it means no strength at all chargeWeak, chargeMediumWeak, charge, chargeMediumStrong, chargeStrong, force, -- weakest drive level, allows test procs to check if device has tristated driveWeak, driveMediumWeak, drive, driveMediumStrong, driveStrong, infinite -- drive for nodes which have infinite current sources }; Level: TYPE = {L, H, X}; LevelSequence: TYPE = REF LevelSequenceRec; LevelSequenceRec: TYPE = RECORD [levels: PACKED SEQUENCE size: NAT OF Level]; BoolSequence: TYPE = REF BoolSequenceRec; BoolSequenceRec: TYPE = RECORD [bools: PACKED SEQUENCE size: NAT OF BOOL]; PortList: TYPE = LIST OF Port; <> CreatePort: PROC [wire: Core.Wire] RETURNS [port: Port]; <<>> InitPort: PROC [wire: Core.Wire, initType: PortType _ b, initDrive: Drive _ none]; WirePortType: PROC [wire: Core.Wire] RETURNS [type: PortType]; PortLeaves: PROC [port: Port] RETURNS [leaves: CARDINAL]; PrintPort: PROC [wire: Core.Wire, port: Port, out: Core.STREAM]; <> CopyPortValue: PROC [from: Port, to: Port]; <> CheckPortValue: PROC [truth: Port, question: Port]; <> <<>> CheckError: SIGNAL; <> EachPortPairProc: TYPE = PROC [onePort: Port, anotherPort: Port] RETURNS [subElements: BOOL _ TRUE, quit: BOOL _ FALSE]; VisitPortPair: PROC [onePort: Port, anotherPort: Port, eachPortPair: EachPortPairProc] RETURNS [quit: BOOL]; <> EachWirePortPairProc: TYPE = PROC [wire: Core.Wire, port: Port] RETURNS [subElements: BOOL _ TRUE, quit: BOOL _ FALSE]; VisitBinding: PROC [wire: Core.Wire, port: Port, eachWirePortPair: EachWirePortPairProc] RETURNS [quit: BOOL]; <> END.