DIRECTORY Core, CoreClasses, CoreCreate, CoreOps, CoreProperties, EU2Utils, Rope, Rosemary, RosemaryUser, Ports; EU2Sim: CEDAR PROGRAM IMPORTS EU2Utils, Rosemary, RosemaryUser, Ports = BEGIN OPEN Core, EU2Utils; Vdd, Gnd, PadVdd, PadGnd, PhA, PhB, VRef, DPRejectB, DPData, -- 32 bits KBus, -- 32 bits EURes3BisPBus3AB, EUWriteToPBus3AB, EUAluOp2AB, -- 4 bits Dragon.ALUOps EUCondSel2AB, -- 4 bits Dragon.CondSelects EUCondition2B, DShA, DShB, DShRd, DShWt, DShIn, DShOut, DHold, DStAd: NAT; testName: ROPE = "EU2Test"; ExerciseRose: PUBLIC PROC [eu2: CellType] RETURNS [sim: Rosemary.Simulation] = { public: Wire _ eu2.public; Vdd _ PortIndex[public, "Vdd"]; Gnd _ PortIndex[public, "Gnd"]; PadVdd _ PortIndex[public, "PadVdd"]; PadGnd _ PortIndex[public, "PadGnd"]; PhA _ PortIndex[public, "PhA"]; PhB _ PortIndex[public, "PhB"]; VRef _ PortIndex[public, "VRef"]; DPRejectB _ PortIndex[public, "DPRejectB"]; DPData _ PortIndex[public, "DPData"]; KBus _ PortIndex[public, "KBus"]; EURes3BisPBus3AB _ PortIndex[public, "EURes3BisPBus3AB"]; EUWriteToPBus3AB _ PortIndex[public, "EUWriteToPBus3AB"]; EUAluOp2AB _ PortIndex[public, "EUAluOp2AB"]; EUCondSel2AB _ PortIndex[public, "EUCondSel2AB"]; EUCondition2B _ PortIndex[public, "EUCondition2B"]; DShA _ PortIndex[public, "DShA"]; DShB _ PortIndex[public, "DShB"]; DShRd _ PortIndex[public, "DShRd"]; DShWt _ PortIndex[public, "DShWt"]; DShIn _ PortIndex[public, "DShIn"]; DShOut _ PortIndex[public, "DShOut"]; DHold _ PortIndex[public, "DHold"]; DStAd _ PortIndex[public, "DStAd"]; [] _ Rosemary.SetFixedWire[public[Vdd], H]; [] _ Rosemary.SetFixedWire[public[Gnd], L]; [] _ Rosemary.SetFixedWire[public[PadVdd], H]; [] _ Rosemary.SetFixedWire[public[PadGnd], L]; [] _ Rosemary.SetFixedWire[public[VRef], H]; [] _ Ports.InitTesterDrive[public[PhA], force]; [] _ Ports.InitTesterDrive[public[PhB], force]; [] _ Ports.InitTesterDrive[public[DPRejectB], force]; [] _ Ports.InitPort[public[DPData], lc]; [] _ Ports.InitTesterDrive[public[DPData], expect]; [] _ Ports.InitPort[public[KBus], lc]; [] _ Ports.InitTesterDrive[public[KBus], force]; [] _ Ports.InitTesterDrive[public[EURes3BisPBus3AB], force]; [] _ Ports.InitTesterDrive[public[EUWriteToPBus3AB], force]; [] _ Ports.InitPort[public[EUAluOp2AB], c]; [] _ Ports.InitTesterDrive[public[EUAluOp2AB], force]; [] _ Ports.InitPort[public[EUCondSel2AB], c]; [] _ Ports.InitTesterDrive[public[EUCondSel2AB], force]; [] _ Ports.InitTesterDrive[public[EUCondition2B], expect]; [] _ Ports.InitTesterDrive[public[DShA], force]; [] _ Ports.InitTesterDrive[public[DShB], force]; [] _ Ports.InitTesterDrive[public[DShRd], force]; [] _ Ports.InitTesterDrive[public[DShWt], force]; [] _ Ports.InitTesterDrive[public[DShIn], force]; [] _ Ports.InitTesterDrive[public[DShOut], none]; [] _ Ports.InitTesterDrive[public[DHold], force]; [] _ Ports.InitPort[public[DStAd], c]; [] _ Ports.InitTesterDrive[public[DStAd], force]; sim _ RosemaryUser.TestProcedureViewer[ cellType: eu2, testButtons: LIST[testName], name: testName, displayWires: RosemaryUser.DisplayCellTypePortLeafWires[eu2], flatten: TRUE, cutSets: LIST["AlpsCell", "EU2Ram"]]; }; EU2Test: RosemaryUser.TestProc = { constAdr: NAT _ EU2Utils.constAdr; junkAdr: NAT _ EU2Utils.junkAdr; PackK: PROC [a, b: NAT _ constAdr, c: NAT _ junkAdr, st3AisC: BOOL _ FALSE, aluL, aluR, st2A: NAT _ 0] RETURNS [k: LONG CARDINAL] ~ { k _ (((((LONG[a]*256+LONG[b])*256+LONG[c])*2+(IF st3AisC THEN 1 ELSE 0))*4+aluL)*8+aluR)*4+st2A; }; Phase: TYPE = {A, B}; DoPh: PROC [ph: Phase] = { p[PhA].b _ ph=A; p[PhB].b _ ph=B; Eval[]; p[PhA].b _ FALSE; p[PhB].b _ FALSE; Eval[]; }; p[DPRejectB].b _ FALSE; p[KBus].lc _ PackK[c: 1]; -- aAdr=bAdr=Const0, cAdr=1, everything else =0 p[EURes3BisPBus3AB].b _ FALSE; -- (fetch) read data from PBus p[EUWriteToPBus3AB].b _ TRUE; -- (store) but don't write onto PBus during PhB p[EUAluOp2AB].c _ 0; -- OR p[EUCondSel2AB].c _ 0; -- false p[DShA].b _ TRUE; -- hack to clean up the ShReg. p[DShB].b _ TRUE; p[DShRd].b _ FALSE; p[DShWt].b _ FALSE; p[DShIn].b _ FALSE; p[DHold].b _ FALSE; p[DStAd].c _ 0; p[DPData].d _ none; FOR c: NAT IN [0..4) DO DoPh[B ! Rosemary.Stop => RESUME]; DoPh[A ! Rosemary.Stop => RESUME]; ENDLOOP; FOR cyles: INT IN [0..10) DO p[DPData].d _ expect; p[DPData].lc _ 0; DoPh[A]; p[DPData].d _ none; DoPh[B]; ENDLOOP; }; RosemaryUser.RegisterTestProc[testName, EU2Test]; END. HEU2Sim.mesa Copyright c 1985 by Xerox Corporation. All rights reversed. Created by Bertrand Serlet July 31, 1985 3:03:17 pm PDT Last edited by Bertrand Serlet June 8, 1986 5:21:11 pm PDT Barth, April 16, 1986 3:05:40 pm PST Louis Monier June 14, 1986 10:50:12 pm PDT Test of EU2 -- Phase-multiplexed on KBus aAdr [0..7] bAdr [8..15] cAdr [16..23] EUSt3AisCBus2BA [24] EUAluLeftSrc1BA [25..26] EUAluRightSrc1BA [27..29] EUStore2ASrc1BA [30..31] -- Test starts here -- read two zeros out of the RAM, OR them, send this on PBus (PhA) and write in RAM[1] -- check the PBus Κ4– "cedar" style˜codešœ ™ Jšœ Οmœ1™˜>Kšœ žœ˜Kšœ žœ˜%—K˜—K˜š‘œ˜"Kšœ žœ˜"Kšœ žœ˜ K˜š‘œžœžœ ˜#Kšœžœ ˜Kšœ žœžœ˜Kš œžœžœžœžœ˜9Kš œ žœžœ žœžœ žœžœ˜`K˜—K˜Kšœžœ ˜š‘œžœ˜Kšœ˜Kšœ˜Jšœ˜Kšœ žœ˜Kšœ žœ˜Jšœ˜K˜K˜—Kšœžœ˜K˜Kšœ /˜IKšœžœ ˜=Kšœžœ /˜MKšœ ˜Kšœ ˜ K˜Kšœ žœ ˜0Kšœ žœ˜Kšœ žœ˜Kšœ žœ˜Kšœ žœ˜K˜Kšœ žœ˜Kšœ˜K˜Kšœ˜K˜šžœžœžœž˜Jšœžœ˜"Jšœžœ˜"Jšžœ˜—K™KšΠlx™K™K™VK™šžœžœžœ ž˜Kšœ˜Kšœ˜Jšœ˜J˜Kšœ˜Jšœ˜Kšžœ˜—Kšœ˜—K˜Kšœ1˜1—Kšžœ˜K˜—…—0¬