DIRECTORY Core, CoreCreate, CoreOps, EU2Inner, EU2ControlAlps, EU2LeafUtils, EU2Utils, LayoutCheckpoint, PWCore, PWCoreRoute; EU2InnerImpl: CEDAR PROGRAM IMPORTS CoreCreate, CoreOps, EU2ControlAlps, EU2LeafUtils, EU2Utils, LayoutCheckpoint, PWCore, PWCoreRoute EXPORTS EU2Inner = BEGIN OPEN EU2Inner, EU2Utils, CoreCreate; CreateEU2Inner: PUBLIC PROC RETURNS [cellType: CellType] = { channelData: PWCoreRoute.ChannelData; public: Wire _ Union[GenPGnEWires[], GenWiresForOnion[], Wires["VRef"]]; Vdd: Wire _ FindWire[public, "Vdd"]; Gnd: Wire _ FindWire[public, "Gnd"]; phA: Wire _ FindWire[public, "phA"]; phB: Wire _ FindWire[public, "phB"]; nPhA: Wire _ FindWire[public, "nPhA"]; nPhB: Wire _ FindWire[public, "nPhB"]; VRef: Wire _ FindWire[public, "VRef"]; enWrtIFUPhA: Wire _ FindWire[public, "enWrtIFUPhA"]; enWrtIFUPhB: Wire _ FindWire[public, "enWrtIFUPhB"]; enWrtPBusPhA: Wire _ FindWire[public, "enWrtPBusPhA"]; enWrtPBusPhB: Wire _ FindWire[public, "enWrtPBusPhB"]; write: Wire _ FindWire[public, "write"]; read: Wire _ FindWire[public, "read"]; hold: Wire _ FindWire[public, "hold"]; dStateAd: Wire _ FindWire[public, "dStateAd"]; onlyInternal, kReg, ramAdr, ctrl8, partOfInternal: Wire; dp, ctrl: CellType; IF EU2Utils.useInnerCheckpoint THEN RETURN [LayoutCheckpoint.Retrieve["EU2Inner"]]; PrintStart["Inner"]; dp _ IF EU2Utils.useDataPathCheckpoint THEN LayoutCheckpoint.Retrieve["EU2DataPath"] ELSE EU2LeafUtils.Extract["EU2DataPath.sch"]; ctrl _ EU2ControlAlps.CreateControl[]; partOfInternal _ GenWiresForRouter[]; kReg _ FindWire[partOfInternal, "kReg"]; ramAdr _ TransferStructure[FindWire[ctrl.public, "ramAdr"], Range[kReg, 0, 24]]; ctrl8 _ TransferStructure[FindWire[ctrl.public, "ctrl8"], Range[kReg, 24, 8]]; onlyInternal _ Union[partOfInternal, Wires[ramAdr, ctrl8]]; channelData _ NEW[PWCoreRoute.ChannelDataRec _ [ inX: TRUE, bottomOrLeftWires: LIST[Vdd, Gnd, phA, phB, nPhA, nPhB, enWrtPBusPhA, enWrtPBusPhB], topOrRightWires: LIST[Vdd, Gnd, enWrtIFUPhA, enWrtIFUPhB, write, read, hold, dStateAd], trunkLayer: "metal2", branchLayer: "metal", extend: TRUE, extendTopOrRight: FALSE, wireWidthProc: PWCoreRoute.GndAndVdd25Met2MinWidth ]]; cellType _ Cell[ name: "EU2Inner", public: public, onlyInternal: onlyInternal, instances: LIST [ Instance[ctrl, ["ramAdr", ramAdr], ["ctrl8", ctrl8], ["carryBAIn", "carryBA"], ["carryABIn", "carryAB"], ["conditionIn", "condition"] ], Instance[dp] ] ]; PWCore.SetLayout[cellType, $Channel, $ChannelData, channelData]; PrintStop["Inner"]; }; TransferStructure: PROC [public, internal: Wire] RETURNS [actual: Wire] = { iPos: NAT _ 0; LeftToRightInWire: PROC [public: Wire] RETURNS [actual: Wire] = { IF public.size=0 THEN { actual _ internal[iPos]; iPos _ iPos + 1; } ELSE { actual _ CoreOps.CreateWires[size: public.size]; FOR subWire: NAT IN [0..public.size) DO actual[subWire] _ LeftToRightInWire[public[subWire]]; ENDLOOP; }; }; actual _ LeftToRightInWire[public]; IF internal.size#iPos THEN ERROR; }; END. τEU2InnerImpl.mesa Copyright c 1985 by Xerox Corporation. All rights reserved. Louis Monier June 14, 1986 5:21:09 pm PDT Bertrand Serlet June 7, 1986 7:34:12 pm PDT -- internal -- internal is flat, and #atomic[public]=#atomic[internal] Κ– "cedar" style˜codešœ™Kšœ Οmœ1™