DIRECTORY Boole, BooleCore, CoreCreate, CoreOps, CoreProperties, Dragon, EU2ControlAlps, EU2LeafUtils, EU2Utils, LayoutCheckpoint, PWCore, PWCoreRoute, RopeList;

EU2ControlAlpsImpl: CEDAR PROGRAM
IMPORTS Boole, BooleCore, CoreCreate, CoreOps, CoreProperties, EU2LeafUtils, EU2Utils, LayoutCheckpoint, PWCore, PWCoreRoute, RopeList
EXPORTS EU2ControlAlps = 
BEGIN OPEN Boole, BooleCore, CoreCreate, EU2ControlAlps, EU2Utils;

ExprProc: TYPE ~ PROC [i: NAT _ 0] RETURNS [Expression];

AppendInput: PROC [public: Wire, wr: WR, inputD: Inputs] RETURNS [ins: Inputs]~ {
AppendOneInput: PROC [wire: Wire] ~ {ins _ CONS[[input: wire, driver: inv], ins]};
inv: CellType _ EU2LeafUtils.AlpsExtract["InputDriver.sch"];
ins _ inputD;
CoreOps.VisitAtomicWires[FindWire[public, wr], AppendOneInput];
};

AppendOutput: PROC [wire: WR, expr: Expression, clock: ROPE _ NIL, outputDrivers: Outputs] RETURNS [Outputs] ~ {
out: CellType _ EU2LeafUtils.AlpsExtract[IF clock=NIL THEN "OutputDriver.sch" ELSE "ClockedOutputDriver.sch"];
RETURN [CONS[
[driver: out, 
pas: IF clock=NIL THEN LIST[["VRef", "VRef"]] 
ELSE LIST[["Clock", clock], ["VRef", "VRef"]], 
output: wire, expr: expr], 
outputDrivers]];
};
AppendState: PROC [wire: WR, expr: Expression, clock: ROPE, outputDrivers: Outputs] RETURNS [Outputs] ~ {
out: CellType _ EU2LeafUtils.AlpsExtract["StateOutputDriver.sch"];
IF clock=NIL THEN ERROR;	-- need a clock to latch the state
RETURN [CONS[
[driver: out, 
pas: LIST[["Latch", clock], ["VRef", "VRef"]], 
output: wire, expr: expr], 
outputDrivers]];
};

-- To be generated by Alps (Ave, Serlet, programatori te salutant!)
CreateRamControl: PUBLIC PROC RETURNS [cellType: CellType] = {
IF EU2Utils.useRamControlCheckpoint THEN RETURN [LayoutCheckpoint.Retrieve["RamControl"]];
BEGIN
inputDrivers: Inputs _ NIL;
outputDrivers: Outputs _ NIL;
expr: Expression _ NIL;
public: Wire _ Union[
GenPGnEWires[], 		-- Vdd and Gnd
GenWiresCtrlToRam[], 		-- all Select lines, nPrech, dRamRead
GenWiresRamToCtrl[], 		-- ramAdr
WireList[LIST["reject", "hold", "read", "write", Seq["dStateAd", 4], "enWrtIFUPhA", "enWrtIFUPhB", "phA", "nPhB", "VRef", 
GenRegSelWire[field],		-- selFieldSrc[0..2)
]]];
dStateAd: Wire _ FindWire[public, "dStateAd"];
ramAdr: Wire _ FindWire[public, "ramAdr"];
aHi: Wire _ ramAdr[a][hi];
bHi: Wire _ ramAdr[b][hi];
cHi: Wire _ ramAdr[c][hi];
aLow: Wire _ ramAdr[a][low];
bLow: Wire _ ramAdr[b][low];
cLow: Wire _ ramAdr[c][low];
cAdr: Wire _ ramAdr[c];
read: Expression _ WireVar[public, "read"];
write: Expression _ WireVar[public, "write"];
reject: Expression _ WireVar[public, "reject"];
nReject: Expression _ Not[reject];
hold: Expression _ WireVar[public, "hold"];
nHold: Expression _ Not[hold];

AppendRamDriver: PROC [output: WR, expr: Expression] ~ {
outputDrivers _ AppendOutput[output , expr, "phA", outputDrivers];
};
IF aLow.size#2 OR bLow.size#2 OR cLow.size#2 THEN ERROR;
IF aHi.size#6 OR bHi.size#6 OR cHi.size#6 THEN ERROR;
inputDrivers _ AppendInput[public, "reject", inputDrivers];	-- 1
inputDrivers _ AppendInput[public, "hold", inputDrivers];	-- 1
inputDrivers _ AppendInput[public, "read", inputDrivers];	-- 1
inputDrivers _ AppendInput[public, "write", inputDrivers];	-- 1
inputDrivers _ AppendInput[public, "dStateAd", inputDrivers];	-- 4
inputDrivers _ AppendInput[public, ramAdr, inputDrivers];	-- 24

outputDrivers _ AppendOutput["enWrtIFUPhA", EqualInt[public, cAdr, IFUAdr], NIL, outputDrivers];
outputDrivers _ AppendOutput["enWrtIFUPhB", false, NIL, outputDrivers];
outputDrivers _ AppendOutput["nPrech", true, "nPhB", outputDrivers];
FOR i: INT IN [0..nRows) DO
AppendRamDriver[Index["selA", i], EqualInt[public, aHi, i]];
AppendRamDriver[Index["selB", i], EqualInt[public, bHi, i]];
expr _ IF i=marAdr/4 THEN Or[reject, EqualInt[public, cHi, i]] 
ELSE And[nReject, EqualInt[public, cHi, i]];
AppendRamDriver[Index["selC", i], expr];
ENDLOOP;
FOR i: INT IN [0..sizeSelLow) DO
AppendRamDriver[Index["selALow", i], EqualInt[public, aLow, i]];
AppendRamDriver[Index["selBLow", i], EqualInt[public, bLow, i]];
expr _ IF i=marAdr MOD 4 THEN Or[reject, EqualInt[public, cLow, i]] 
ELSE And[nReject, EqualInt[public, cLow, i]];
AppendRamDriver[Index["selCLow", i], expr];
ENDLOOP;
outputDrivers _ AppendOutput["selFieldSrc[0]", 
And[nReject, nHold, EqualInt[public, cAdr, fieldAdr]], "phA", outputDrivers];
outputDrivers _ AppendOutput["selFieldSrc[1]", 
And[write, EqualInt[public, dStateAd, field]], NIL, outputDrivers];
outputDrivers _ AppendOutput["selFieldSrc[2]", 
And[read, EqualInt[public, dStateAd, field]], NIL, outputDrivers];
outputDrivers _ AppendOutput["dRamRead", 
And[read, EqualInt[public, dStateAd, ramA]], NIL, outputDrivers];
cellType _ AlpsCell[
name: "RamControl",
public: public,
inputs: inputDrivers,
outputs: outputDrivers,
props: CoreProperties.Props[[$ContactPolyMetal2, NEW[INT _ 20]]]
];
END;
};

CreateBothAlps: PUBLIC PROC RETURNS [cellType: CellType] ~ {

ctrlTop: CellType _ CreateCondControl[];
ctrlBot: CellType _ CreateDPControl[];
public: Wire _ Union[
CopyAndDeleteNames[ctrlTop.public, LIST["Vdd", "Gnd", "VRef", "phB", "res0", "carryOut", "lz", "kernal", "il"]], 
CopyAndDeleteNames[ctrlBot.public]
];
Vdd: Wire _ FindWire[public, "Vdd"];
Gnd: Wire _ FindWire[public, "Gnd"];
condSel: Wire _ FindWire[public, "condSel"];
reject: Wire _ FindWire[public, "reject"];
hold: Wire _ FindWire[public, "hold"];
read: Wire _ FindWire[public, "read"];
write: Wire _ FindWire[public, "write"];
res3BisP: Wire _ FindWire[public, "res3BisP"];
writePBus: Wire _ FindWire[public, "writePBus"];
aluOp: Wire _ FindWire[public, "aluOp"];
dStateAd: Wire _ FindWire[public, "dStateAd"];
il: Wire _ FindWire[public, "il"];
lz: Wire _ FindWire[public, "lz"];
kernal: Wire _ FindWire[public, "kernal"];
zero: Wire _ FindWire[public, "zero"];
ctrl8: Wire _ FindWire[public, "ctrl8"];
opL: Wire _ FindWire[public, "opL"];
opR: Wire _ FindWire[public, "opR"];
res: Wire _ FindWire[public, "res"];
carryOut: Wire _ FindWire[public, "carryOut"];
shift: Wire _ FindWire[public, "shift"];
carryABIn: Wire _ FindWire[public, "carryABIn"];
carryBAIn: Wire _ FindWire[public, "carryBAIn"];
conditionIn: Wire _ FindWire[public, "conditionIn"];
channelData: PWCoreRoute.ChannelData _ NEW[PWCoreRoute.ChannelDataRec _ [
inX: FALSE,
bottomOrLeftWires: LIST[Vdd, Gnd, condSel, reject, res3BisP, writePBus, aluOp],
topOrRightWires: LIST[hold, read, write, dStateAd, il, lz, kernal, zero, ctrl8, opL, opR, res, carryOut, shift, carryABIn, carryBAIn, conditionIn],
trunkLayer: "metal",
branchLayer: "metal2",
extendTopOrRight: FALSE,
extend: TRUE,
wireWidthProc: PWCoreRoute.GndAndVdd25Met2MinWidth
]];
cellType _ Cell[
name: "BothAlps",
public: public,
instances: LIST [
Instance[name: "BottomAlps", 
type: PWCore.RotateCellType[ctrlBot, $FlipY]],
Instance[name: "TopAlps", 
type: ctrlTop, 
pa1: ["res0", "res[0]"]]
]
];
PWCore.SetLayout[cellType, $Channel, $ChannelData, channelData];
};

CreateCondControl: PUBLIC PROC RETURNS [cellType: CellType] ~ {
CondIs: PROC [cond: Dragon.CondSelects] RETURNS [expr: Expression] ~ {
expr _ EqualInt[public, condSel, Dragon.CondSelects[cond].ORD];
};
public: Wire _ Wires["Vdd", "Gnd", "phB", "condition", "VRef", 
Seq["condSel", sizeCondSelects], 	-- from pads
"zero", "carryOut", "res0",	-- from data path
"kernal", "lz", "il"];		-- output of DPControl alps block

condSel: Wire _ FindWire[public, "condSel"];
zero: Expression _ WireVar[public, "zero"];
lz: Expression _ WireVar[public, "lz"];
le: Expression _ Or[lz, zero];
kernal: Expression _ WireVar[public, "kernal"];
res0: Expression _ WireVar[public, "res0"];
overflow: Expression _ Xor[lz, res0];
carryOut: Expression _ WireVar[public, "carryOut"];
il: Expression _ WireVar[public, "il"];

cond: Expression _ OrList[LIST[
And[CondIs[EZ], zero],
And[CondIs[LZ], lz],
And[CondIs[LE], le],
And[CondIs[AddressCheckFault], kernal],
And[CondIs[NE], Not[zero]],
And[CondIs[GE], Not[lz]],
And[CondIs[GZ], Not[le]],
And[CondIs[OvFl], overflow],
And[CondIs[BC], Not[carryOut]],
And[CondIs[IL], il],
And[CondIs[NotBC], carryOut],
And[CondIs[NotIL], Not[il]],
And[CondIs[ModeFault], true]
]];

inputDrivers: Inputs _ NIL;
outputDrivers: Outputs _ NIL;

IF EU2Utils.useCondControlCheckpoint THEN RETURN [LayoutCheckpoint.Retrieve["CondControl"]];

inputDrivers _ AppendInput[public, "condSel", inputDrivers];	-- 4
inputDrivers _ AppendInput[public, "zero", inputDrivers];	-- 1
inputDrivers _ AppendInput[public, "carryOut", inputDrivers];	-- 1
inputDrivers _ AppendInput[public, "res0", inputDrivers];	-- 1
inputDrivers _ AppendInput[public, "kernal", inputDrivers];	-- 1
inputDrivers _ AppendInput[public, "lz", inputDrivers];	-- 1
inputDrivers _ AppendInput[public, "il", inputDrivers];	-- 1
outputDrivers _ AppendState["condition", cond, "phB", outputDrivers];

cellType _ AlpsCell[
name: "CondControl",
public: public,
inputs: inputDrivers,
outputs: outputDrivers
];

};

CreateDPControl: PUBLIC PROC RETURNS [cellType: CellType] = {
IF EU2Utils.useDPControlCheckpoint THEN RETURN [LayoutCheckpoint.Retrieve["DPControl"]];
BEGIN
MakeSelExpr: PROC [reg: PipeRange, exprProc: ExprProc, clock: ROPE _ NIL] ~ {
size: NAT _ sources[reg].sizeSel;
FOR i: INT IN [0..size) DO
outputDrivers _ AppendOutput[
wire: Index[sources[reg].nameSel, i], 
expr: exprProc[i],
clock: clock,
outputDrivers: outputDrivers];
ENDLOOP;
outputDrivers _ AppendOutput[
wire: Index[sources[reg].nameSel, size], 
expr: And[write, EqualInt[public, dStateAd, reg]],
clock: NIL,
outputDrivers: outputDrivers];
outputDrivers _ AppendOutput[
wire: Index[sources[reg].nameSel, size+1], 
expr: And[read, EqualInt[public, dStateAd, reg]],
clock: NIL,
outputDrivers: outputDrivers];
};
inputDrivers: Inputs _ NIL;
outputDrivers: Outputs _ NIL;
public: Wire _ Union[
WireList[LIST["Vdd", "Gnd", "phA", "phB", "carryBA", "carryBAIn", "carryAB", "carryABIn", "kernal", "il", "lz", "enWrtPBusPhA", "enWrtPBusPhB", "conditionIn", Seq["ctrl8", 8], "writePBus", "res3BisP", "reject", Seq["aluOp", sizeALUOps], "hold", "read", "write", Seq["dStateAd", 4], "VRef" ]],
Wires[GenRegSelWire[left],
GenRegSelWire[right],
GenRegSelWire[st2A],
GenRegSelWire[st2B],
GenRegSelWire[st3A],
GenRegSelWire[kReg],
GenRegSelWire[r2B],
GenRegSelWire[r3A],
GenRegSelWire[r3B],
GenRegSelWire[dataIn],
Seq["selcBusSrc", 3]],
GenWiresCtrlToALU[],
Wires["carryOut", Seq["res", 8], Seq["opL", 3], Seq["opR", 3], Seq["shift", 6], Seq["sh", wordSize+1]]];
ctrl8: Wire _ FindWire[public, "ctrl8"];
leftSrc: Wire _ Range[ctrl8, 1, 2];
rightSrc: Wire _ Range[ctrl8, 3, 3];
st2ASrc: Wire _ Range[ctrl8, 6, 2];
res: Wire _ FindWire[public, "res"];
opL: Wire _ FindWire[public, "opL"];
opR: Wire _ FindWire[public, "opR"];
shift: Wire _ FindWire[public, "shift"];
aluOp: Wire _ FindWire[public, "aluOp"];
dStateAd: Wire _ FindWire[public, "dStateAd"];
reject: Expression _ WireVar[public, "reject"];	-- latched on PhB in the pad
nReject: Expression _ Not[reject];
read: Expression _ WireVar[public, "read"];
write: Expression _ WireVar[public, "write"];
hold: Expression _ WireVar[public, "hold"];
nHold: Expression _ Not[hold];
fetch: Expression _ WireVar[public, "res3BisP"];
store: Expression _ WireVar[public, "writePBus"];
st3AisC: Expression _ WireVar[public, ctrl8[0]];
opL0: Expression _ WireVar[public, opL[0]];
opR0: Expression _ WireVar[public, opR[0]];
carryOut: Expression _ WireVar[public, "carryOut"];
carryBAIn: Expression _ WireVar[public, "carryBAIn"];
carryABIn: Expression _ WireVar[public, "carryABIn"];
conditionIn: Expression _ WireVar[public, "conditionIn"];
LeftExpr: ExprProc = {RETURN[And[nReject, nHold, EqualInt[public, leftSrc, i]]]};
RightExpr: ExprProc = {RETURN[And[nReject, nHold, EqualInt[public, rightSrc, i]]]};
St2AExpr: ExprProc = {RETURN[And[nReject, nHold, EqualInt[public, st2ASrc, i]]]};
R3AExpr: ExprProc = {RETURN[And[nReject, nHold]]};
St3AExpr: ExprProc = {RETURN[
SELECT i FROM
0 => And[nReject, nHold, Not[st3AisC]],
1 => And[nReject, nHold, st3AisC],
ENDCASE => ERROR]};

KRegExpr: ExprProc = {RETURN[nHold]};
R2BExpr: ExprProc = {RETURN[
SELECT i FROM
0 => And[nHold, Nor[				-- aluOut	
OpIs[FOP],			-- neither FOP
OpIs[BndChk]]],		-- nor BndChk
1 => And[nHold, OpIs[FOP]],	-- fuOut
2 => And[nHold, OpIs[BndChk]],	-- left
ENDCASE => ERROR]};
St2BExpr: ExprProc = {RETURN[nHold]};
R3BExpr: ExprProc = {RETURN[nHold]};
DataInExpr: ExprProc = {RETURN[nHold]};

CBusExpr: ExprProc = {RETURN[	-- use the non-latched reject and a simple driver, no clock!!!
SELECT i FROM
0 => Nand[nReject, store, fetch],		-- r3B
1 => And[nReject, nHold, fetch],		-- dataIn
2 => Or[EqualInt[public, dStateAd, cBus], Not[read]],
ENDCASE => ERROR]};
ShExpr: ExprProc = {RETURN[EqualInt[public, shift, i]]};
CarryInExpr: ExprProc = {RETURN[
OrList[LIST[	-- Or, And, LAdd, Xor, FOP, VAdd and VAdd2 -> false
And[OpIs[VSub], true], 	-- I hope Alps does some simplification!!!
And[OpIs[LSub], true], 
And[OpIs[BndChk], true], 
And[OpIs[SAdd], carryABIn], 	-- prev
And[OpIs[SSub], Not[carryABIn]], 	-- nprev
And[OpIs[UAdd], carryABIn], 
And[OpIs[USub], Not[carryABIn]]
]]
]};
CarryBAExpr: ExprProc = {RETURN[
OrList[LIST[	-- SAdd, SSub, LAdd and LSub -> false
And[OpIs[VAdd], carryABIn], 
And[OpIs[VAdd2], carryABIn], 
And[OpIs[VSub], carryABIn], 
And[OpIs[BndChk], carryABIn], 
And[OpIs[Or], carryABIn], 
And[OpIs[And], carryABIn], 
And[OpIs[Xor], carryABIn], 
And[OpIs[FOP], carryABIn], 	-- prev
And[OpIs[UAdd], carryOut], 	-- comp
And[OpIs[USub], Not[carryOut]]	-- ncomp
]]
]};
CarryABExpr: ExprProc = {RETURN[
If[And[nReject, Not[conditionIn]], carryBAIn, carryABIn] ]};
OpExpr: ExprProc = {
RETURN[SELECT i FROM	-- add	sub	xor	or	and
0 => Not[InSet[sub]],	--  1	0	1	1	1
1 => InSet[sub, and],	--  0	1	0	0	1
2 => InSet[add, xor],	--  1	0	1	0	0
3 => Not[InSet[add]],	--  0	1	1	1	1
4 => Not[InSet[sub]],	--  1	0	1	1	1
ENDCASE => ERROR];
};
OpType: TYPE = {add, sub, xor, or, and, none};
OpIs: PROC [op: Dragon.ALUOps] RETURNS [expr: Expression] ~ {
expr _ EqualInt[public, aluOp, Dragon.ALUOps[op].ORD];
};
InSet: PROC [t1, t2: OpType _ none] RETURNS [expr: Expression] ~ {
AddMatchType: PROC [op: OpType] RETURNS [expr: Expression]~ {
expr _ SELECT op FROM
add => And[OpIs[VAdd2], OpIs[SAdd], OpIs[LAdd], OpIs[VAdd], OpIs[UAdd]],
sub => And[OpIs[BndChk], OpIs[SSub], OpIs[LSub], OpIs[VSub], OpIs[USub]],
xor => OpIs[Xor], 
or => And[OpIs[Or], OpIs[FOP]],
and => OpIs[And], 
ENDCASE => ERROR;
};
expr _ AddMatchType[t1];
IF t2#none THEN expr _ And[expr, AddMatchType[t2]];
};
IsLispInt: PROC [threeBit: Wire] RETURNS [Expression] ~ {
RETURN[Or[EqualInt[public, threeBit, 0], EqualInt[public, threeBit, 7]]];
};

KernalExpr: ExprProc = {RETURN[EqualInt[public, res, 0]]};
ILExpr: ExprProc = {RETURN[Nand[IsLispInt[Range[res, 0, 3]], IsLispInt[opL], IsLispInt[opR]]]};
LZExpr: ExprProc = {RETURN[Xor[Xor[carryOut, opL0], opR0]]};
WrPBusPhAExpr: ExprProc = {RETURN[And[nReject, nHold]]};
WrPBusPhBExpr: ExprProc = {RETURN[And[store, nHold]]};

inputDrivers _ AppendInput[public, "reject", inputDrivers];		-- 1
inputDrivers _ AppendInput[public, "hold", inputDrivers];		-- 1 
inputDrivers _ AppendInput[public, "write", inputDrivers];		-- 1
inputDrivers _ AppendInput[public, "read", inputDrivers];		-- 1
inputDrivers _ AppendInput[public, "res3BisP", inputDrivers];		-- 1
inputDrivers _ AppendInput[public, "writePBus", inputDrivers];	-- 1
inputDrivers _ AppendInput[public, "aluOp", inputDrivers];		-- 4
inputDrivers _ AppendInput[public, "dStateAd", inputDrivers];		-- 4
inputDrivers _ AppendInput[public, "conditionIn", inputDrivers];	-- 1
inputDrivers _ AppendInput[public, "carryBAIn", inputDrivers];	-- 1
inputDrivers _ AppendInput[public, "carryABIn", inputDrivers];	-- 1
inputDrivers _ AppendInput[public, "ctrl8", inputDrivers];		-- 8
inputDrivers _ AppendInput[public, "shift", inputDrivers];		-- 6
inputDrivers _ AppendInput[public, "carryOut", inputDrivers];		-- 1
inputDrivers _ AppendInput[public, "res", inputDrivers];		-- 8
inputDrivers _ AppendInput[public, "opL", inputDrivers];		-- 3
inputDrivers _ AppendInput[public, "opR", inputDrivers];		-- 3

outputDrivers _ AppendOutput["enWrtPBusPhA", WrPBusPhAExpr[], , outputDrivers];
outputDrivers _ AppendOutput["enWrtPBusPhB", WrPBusPhBExpr[], , outputDrivers];
MakeSelExpr[dataIn, DataInExpr, "phB"];
outputDrivers _ AppendOutput[Index["selcBusSrc", 0], CBusExpr[0], , outputDrivers];
outputDrivers _ AppendOutput[Index["selcBusSrc", 1], CBusExpr[1], , outputDrivers];
outputDrivers _ AppendOutput[Index["selcBusSrc", 2], CBusExpr[2], , outputDrivers];
MakeSelExpr[r3B, R3BExpr, "phB"];
MakeSelExpr[r3A, R3AExpr, "phA"];
MakeSelExpr[st3A, St3AExpr, "phA"];
MakeSelExpr[st2B, St2BExpr, "phB"];
FOR i: NAT DECREASING IN [0..wordSize+1) DO
outputDrivers _ AppendOutput[Index["sh", i], ShExpr[i], NIL, outputDrivers];
ENDLOOP;
MakeSelExpr[r2B, R2BExpr, "phB"];
FOR i: NAT IN [0..5) DO
outputDrivers _ AppendOutput[Index["op", i], OpExpr[i], NIL, outputDrivers];
ENDLOOP;
outputDrivers _ AppendOutput["carryIn", CarryInExpr[], NIL, outputDrivers];
MakeSelExpr[st2A, St2AExpr, "phA"];
MakeSelExpr[left, LeftExpr, "phA"];
MakeSelExpr[right, RightExpr, "phA"];
MakeSelExpr[kReg, KRegExpr, "phB"];
outputDrivers _ AppendState["carryBA", CarryBAExpr[], "phB", outputDrivers];
outputDrivers _ AppendState["carryAB", CarryABExpr[], "phA", outputDrivers];
outputDrivers _ AppendOutput["il", ILExpr[], NIL, outputDrivers];
outputDrivers _ AppendOutput["lz", LZExpr[], NIL, outputDrivers];
outputDrivers _ AppendOutput["kernal", KernalExpr[], NIL, outputDrivers];

cellType _ AlpsCell[
name: "DPControl",
public: public,
inputs: inputDrivers,
outputs: outputDrivers, 
props: CoreProperties.Props[[$ContactPolyMetal2, NEW[INT _ 20]]]
];
END;
};

CopyAndDeleteNames: PROC [public: Wire, names: LIST OF ROPE _ NIL] RETURNS [copiedAndDeleted: Wire] ~ {
listWires: LIST OF Wire _ NIL;
FOR i: NAT IN [0 .. public.size) DO
name: ROPE _ CoreOps.GetShortWireName[public[i]];
IF ~RopeList.Memb[names, name] THEN listWires _ CONS[CoreOps.CopyWire[public[i]], listWires];
ENDLOOP;
copiedAndDeleted _ CoreOps.CreateWire[listWires];
};

CreateControl: PUBLIC PROC RETURNS [cellType: CellType] ~ {
IF EU2Utils.useControlCheckpoint THEN RETURN [LayoutCheckpoint.Retrieve["Control"]];
BEGIN
ctrlTop: CellType _ CreateRamControl[];
ctrlBot: CellType _ CreateBothAlps[];
public: Wire _ Union[
CopyAndDeleteNames[ctrlTop.public, LIST["Vdd", "Gnd", "VRef", "reject", "hold", "read", "write", "dStateAd", "phA"]], 
CopyAndDeleteNames[ctrlBot.public]
];
condition: Wire _ FindWire[public, "condition"];
Vdd: Wire _ FindWire[public, "Vdd"];
Gnd: Wire _ FindWire[public, "Gnd"];
reject: Wire _ FindWire[public, "reject"];
hold: Wire _ FindWire[public, "hold"];
read: Wire _ FindWire[public, "read"];
write: Wire _ FindWire[public, "write"];
dStateAd: Wire _ FindWire[public, "dStateAd"];
ramAdr: Wire _ FindWire[public, "ramAdr"];

channelData: PWCoreRoute.ChannelData _ NEW[PWCoreRoute.ChannelDataRec _ [
inX: FALSE,
bottomOrLeftWires: LIST[Vdd, Gnd, reject, condition],
topOrRightWires: LIST[ramAdr, hold, read, write, dStateAd, condition],
trunkLayer: "metal",
branchLayer: "metal2",
extendTopOrRight: FALSE,
extend: TRUE,
wireWidthProc: PWCoreRoute.GndAndVdd25Met2MinWidth
]];
cellType _ Cell[
name: "Control",
public: public,
instances: LIST [
Instance[name: "BottomAlps", type: ctrlBot],
Instance[name: "TopAlps", type: ctrlTop]
]
];
PWCore.SetLayout[cellType, $Channel, $ChannelData, channelData];
END;
};

END.



ΚEU2ControlAlpsImpl.mesa
Copyright c 1985 by Xerox Corporation.  All rights reserved.
Louis Monier June 14, 1986 5:18:37 pm PDT
Bertrand Serlet June 14, 1986 10:35:55 pm PDT
-- public
-- All the wires used as inputs (numbers)
-- Expressions (booleans)

-- Input inverters to the Alps blocks
-- Enable Write on the KBus (IFU side); by luck, same timing as ram
-- enWrtIFUPhA _ cAdr=IFUAdr
-- enWrtIFUPhB _ false (if no // debug, never used, so could be removed)

-- Precharge of the ram
-- nPrech _ nPhB

-- Output drivers, all of the same type: they follow PhA
-- selHi[i][a] _ aAdrH=i
-- selHi[i][b] _ bAdrH=i
-- selHi[i][c] _ (cAdrH=i).~reject	for i#marAdr/4
-- selHi[marAdr/4][c] _ (cAdrH=i)+reject
-- selLow[i][a] _ aAdrL=i
-- selLow[i][b] _ bAdrL=i
-- selLow[i][c] _ (cAdrL=i).~reject	for i#marAdr MOD 4
-- selHi[marAdr MOD 4][c] _ (cAdrL=i)+reject

-- Control for Field register; located here because it requires cAdr; also same timing as ram
-- selFieldSrc[0] _ (cAdr=fieldAdr).~reject.~hold.PhA
-- selFieldSrc[1] _ (dStateAd=field).write
-- selFieldSrc[2] _ (dStateAd=field).read

-- reading the ram while debugging
-- selFieldSrc[2] _ (dStateAd=ramA).read

And[CondIs[False], false],
-- Creates the control for the bottom of the Datapath
-- All the wires used as inputs (numbers)
-- Expressions (booleans)

-- PhA latches
selLeftSrc[i] _ PhA . (leftSrc=i) . ~reject . ~hold
-- selRightSrc[i] _ PhA . (rightSrc=i) . ~reject . ~hold
-- selSt2ASrc[i] _ PhA . (st2ASrc=i) . ~reject . ~hold
-- selRes3ABSrc _ PhA . ~reject . ~hold
-- selSt3ABSrc[st2B] _ PhA . ~st3AisC . ~reject . ~hold
-- selSt3ABSrc[cBus] _ PhA . st3AisC . ~reject . ~hold
-- PhB latches
-- selKRegAdr _ PhB . ~hold
-- selRes2BASrc[aluOut] _ PhB . ~hold . (aluOp=FOP)
-- selRes2BASrc[fuOut] _ PhB . ~hold . (aluOp#FOP)
-- selRes2BASrc[left] _ PhB . ~hold . (aluOp=BndChk)
-- selSt2BASrc _ PhB . ~hold
-- selRes3BASrc[tBus] _ PhB . ~hold
-- selDataInSrc _ PhB . ~hold
-- Special guys
-- selCBusSrc[r3B] _ (reject + ~fetch + ~store)
-- selCBusSrc[dataIn] _ ~reject . ~hold . fetch
-- selCBusSrc[enW] _ (dStAd=cBus) + ~read

-- Field Unit
-- sh[i] _ (shift=i)

-- ALU
-- carryAB _ IF ~reject AND ~condition THEN carryBA ELSE carryAB
-- enWrtPBusPhA _ ~reject AND ~hold
-- enWrtPBusPhB _ store AND ~hold

-- Input to control in order
-- Input Drivers for the (few) signals coming straight from the pads
-- Input Drivers for the signals coming from the Data Path
-- Outputs to Data path in order: bottom ones first
-- To pad frame
-- Bottom Registers
-- Field unit control
-- res2BA Register
-- ALU control
-- Top Registers
-- Carry feedback 
-- Sub-expressions to compute Condition

-- Generate the block Alps
-- To build the public
-- goes throuh
-- out to the left
-- out to the right
Κ/–

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