C0 W0 12 0 W1 0 1 A0 CoreName r R0 "Vdd" W2 0 1 A0 r R1 "Gnd" W3 0 1 A0 r R2 "phB" W4 0 1 A0 r R3 "condition" W5 0 1 A0 r R4 "VRef" W6 4 1 A0 r R5 "condSel" W7 0 0 W8 0 0 W9 0 0 WA 0 0 WB 0 1 A0 r R6 "zero" WC 0 1 A0 r R7 "carryOut" WD 0 1 A0 r R8 "res0" WE 0 1 A0 r R9 "kernal" WF 0 1 A0 r RA "lz" W10 0 1 A0 r RB "il" 3 A0 r RC "CondControl" A1 NbIn i 10 A2 Layout a A3 FullAlpsCell RD "Record" 11 W11 13 0 W1 W2 W3 W4 W5 W6 WB WC WD WE WF W10 W12 10 1 A0 r RE "PlusMinusInputs" W13 2 1 A0 r RB W14 0 1 A0 r RF "Plus" W15 0 1 A0 r R10 "Minus" W16 2 1 A0 r RA W17 0 1 A0 r RF W18 0 1 A0 r R10 W19 2 1 A0 r R9 W1A 0 1 A0 r RF W1B 0 1 A0 r R10 W1C 2 1 A0 r R8 W1D 0 1 A0 r RF W1E 0 1 A0 r R10 W1F 2 1 A0 r R7 W20 0 1 A0 r RF W21 0 1 A0 r R10 W22 2 1 A0 r R6 W23 0 1 A0 r RF W24 0 1 A0 r R10 W25 2 1 A0 r R11 "condSel[3]" W26 0 1 A0 r RF W27 0 1 A0 r R10 W28 2 1 A0 r R12 "condSel[2]" W29 0 1 A0 r RF W2A 0 1 A0 r R10 W2B 2 1 A0 r R13 "condSel[1]" W2C 0 1 A0 r RF W2D 0 1 A0 r R10 W2E 2 1 A0 r R14 "condSel[0]" W2F 0 1 A0 r RF W30 0 1 A0 r R10 W31 4 0 W13 W10 W2 W1 0 C1 W0 4 0 W1 2 1 A0 r R15 "Output" W2 0 1 A0 r RF W3 0 1 A0 r R10 W4 0 1 A0 r R16 "Input" W5 0 1 A0 r R1 W6 0 1 A0 r R0 2 A0 r R17 "InputDriver" A2 a A4 Get RD 2 W7 4 0 W1 W4 W6 W5 W8 4 0 W6 W5 W4 W3 0 C2 W0 4 0 W1 0 2 A0 r R0 A5 PortData l n W2 0 2 A0 r R1 A5 l n W3 0 2 A0 r R16 A5 l n W4 0 2 A0 r R18 "nOutput" A5 l d 3 A0 r R19 "Inverter" A6 RoseBehave r R19 A7 RoseCutSet lor 1 R1A "JustAboveTransistors" RD 2 W0 W5 3 0 W3 W1 W4 0 C3 W0 3 0 W1 0 1 A0 r R1B "gate" W2 0 1 A0 r R1C "ch1" W3 0 1 A0 r R1D "ch2" 1 A8 RoseTransistorSize d R1E "Transistor" pE 2 30 W6 3 0 W3 W4 W2 0 C4 W0 3 0 W1 0 1 A0 r R1B W2 0 1 A0 r R1C W3 0 1 A0 r R1D 1 A8 d R1E nE 2 12 W9 4 0 W6 W5 W3 W2 0 C2 W32 4 0 W16 WF W2 W1 0 C1 W33 4 0 W19 WE W2 W1 0 C1 W34 4 0 W1C WD W2 W1 0 C1 W35 4 0 W1F WC W2 W1 0 C1 W36 4 0 W22 WB W2 W1 0 C1 W37 4 0 W25 WA W2 W1 0 C1 W38 4 0 W28 W9 W2 W1 0 C1 W39 4 0 W2B W8 W2 W1 0 C1 W3A 4 0 W2E W7 W2 W1 0 C1 W3B 6 0 W3 W5 W12 W4 W2 W1 0 C5 W0 6 0 W1 0 1 A0 r R1F "Latch" W2 0 1 A0 r R4 W3 10 1 A0 r R16 W4 2 1 A0 r RB W5 0 1 A0 r RF W6 0 1 A0 r R10 W7 2 1 A0 r RA W8 0 1 A0 r RF W9 0 1 A0 r R10 WA 2 1 A0 r R9 WB 0 1 A0 r RF WC 0 1 A0 r R10 WD 2 1 A0 r R8 WE 0 1 A0 r RF WF 0 1 A0 r R10 W10 2 1 A0 r R7 W11 0 1 A0 r RF W12 0 1 A0 r R10 W13 2 1 A0 r R6 W14 0 1 A0 r RF W15 0 1 A0 r R10 W16 2 1 A0 r R11 W17 0 1 A0 r RF W18 0 1 A0 r R10 W19 2 1 A0 r R12 W1A 0 1 A0 r RF W1B 0 1 A0 r R10 W1C 2 1 A0 r R13 W1D 0 1 A0 r RF W1E 0 1 A0 r R10 W1F 2 1 A0 r R14 W20 0 1 A0 r RF W21 0 1 A0 r R10 W22 0 1 A0 r R15 W23 0 1 A0 r R1 W24 0 1 A0 r R0 1 A2 a A9 AlpsRow RD 2 W25 7 0 W1 W2 W3 W22 W23 W24 W26 2 1 A0 r R20 "OutputPlusMinus" W27 0 1 A0 r RF W28 0 1 A0 r R10 W29 4 0 W3 W26 W23 W24 0 C6 W0 4 0 W1 10 1 A0 r R16 W2 2 1 A0 r RB W3 0 2 A0 r RF A5 l n W4 0 2 A0 r R10 A5 l n W5 2 1 A0 r RA W6 0 2 A0 r RF A5 l n W7 0 2 A0 r R10 A5 l n W8 2 1 A0 r R9 W9 0 2 A0 r RF A5 l n WA 0 2 A0 r R10 A5 l n WB 2 1 A0 r R8 WC 0 2 A0 r RF A5 l n WD 0 2 A0 r R10 A5 l n WE 2 1 A0 r R7 WF 0 2 A0 r RF A5 l n W10 0 2 A0 r R10 A5 l n W11 2 1 A0 r R6 W12 0 2 A0 r RF A5 l n W13 0 2 A0 r R10 A5 l n W14 2 1 A0 r R11 W15 0 2 A0 r RF A5 l n W16 0 2 A0 r R10 A5 l n W17 2 1 A0 r R12 W18 0 2 A0 r RF A5 l n W19 0 2 A0 r R10 A5 l n W1A 2 1 A0 r R13 W1B 0 2 A0 r RF A5 l n W1C 0 2 A0 r R10 A5 l n W1D 2 1 A0 r R14 W1E 0 2 A0 r RF A5 l n W1F 0 2 A0 r R10 A5 l n W20 2 1 A0 r R15 W21 0 2 A0 r RF A5 l n W22 0 2 A0 r R10 A5 l n W23 0 2 A0 r R1 A5 l n W24 0 2 A0 r R0 A5 l n 1 A7 lor 1 R21 "AlpsCell" R22 "Alps" R23 "Not[If[condSel[3], If[condSel[2], If[condSel[1], If[condSel[0], 1, Not[If[lz, 1, zero]]], If[condSel[0], 0, If[lz, 1, zero]]], If[condSel[1], If[condSel[0], carryOut, Not[zero]], If[condSel[0], Not[carryOut], zero]]], If[condSel[2], If[condSel[1], If[condSel[0], Not[il], Not[lz]], If[condSel[0], il, lz]], If[condSel[1], If[condSel[0], 0, kernal], If[condSel[0], If[lz, Not[res0], res0], 0]]]]]" 10 RB RA R9 R8 R7 R6 R11 R12 R13 R14 13 W2A 6 0 W2 W1 W24 W22 W26 W23 0 C7 W0 6 0 W1 0 1 A0 r R4 W2 0 1 A0 r R1F W3 0 1 A0 r R0 W4 0 1 A0 r R15 W5 2 1 A0 r R16 W6 0 1 A0 r RF W7 0 1 A0 r R10 W8 0 1 A0 r R1 2 A0 r R24 "StateOutputDriver" A2 a A4 RD 8 W9 10 0 W2 WA 0 0 W5 WB 0 0 W8 W1 W3 W4 WC 0 0 WD 0 0 WE 3 0 W1 W7 WA 0 C8 W0 3 0 W1 0 1 A0 r R1B W2 0 1 A0 r R1C W3 0 1 A0 r R1D 0 R1E nE 2 8 WF 3 0 W1 W6 WB 0 C8 W10 3 0 W6 W3 WA 0 C9 W0 3 0 W1 0 1 A0 r R1B W2 0 1 A0 r R1C W3 0 1 A0 r R1D 1 A8 dw R1E pE 2 24 W11 3 0 W7 WB W3 0 C9 W12 4 0 W3 W8 WB WC 0 CA W0 4 0 W1 0 2 A0 r R0 A5 l n W2 0 2 A0 r R1 A5 l n W3 0 2 A0 r R16 A5 l n W4 0 2 A0 r R18 A5 l d 3 A0 r R19 A6 r R19 A7 lor 1 R1A RD 2 W0 W5 3 0 W3 W1 W4 0 CB W0 3 0 W1 0 1 A0 r R1B W2 0 1 A0 r R1C W3 0 1 A0 r R1D 1 A8 d R1E pE 2 10 W6 3 0 W3 W4 W2 0 CC W0 3 0 W1 0 1 A0 r R1B W2 0 1 A0 r R1C W3 0 1 A0 r R1D 1 A8 d R1E nE 2 4 W13 3 0 W2 WC WD 0 CD W0 3 0 W1 0 1 A0 r R1B W2 0 1 A0 r R1C W3 0 1 A0 r R1D 0 R1E nE 2 12 W14 4 0 W3 W8 W4 WD 0 CE W0 4 0 W1 0 2 A0 r R0 A5 l n W2 0 2 A0 r R1 A5 l n W3 0 2 A0 r R16 A5 l n W4 0 2 A0 r R18 A5 l dw 3 A0 r R19 A6 r R19 A7 lor 1 R1A RD 2 W0 W5 3 0 W3 W1 W4 0 CF W0 3 0 W1 0 1 A0 r R1B W2 0 1 A0 r R1C W3 0 1 A0 r R1D 1 A8 dw R1E pE 2 3 W6 3 0 W3 W4 W2 0 C10 W0 3 0 W1 0 1 A0 r R1B W2 0 1 A0 r R1C W3 0 1 A0 r R1D 1 A8 dw R1E nE 2 3 W15 4 0 W3 W8 WD W4 0 C11 W0 4 0 W1 0 2 A0 r R0 A5 l n W2 0 2 A0 r R1 A5 l n W3 0 2 A0 r R16 A5 l n W4 0 2 A0 r R18 A5 l d 3 A0 r R19 A6 r R19 A7 lor 1 R1A RD 2 W0 W5 3 0 W3 W1 W4 0 C12 W0 3 0 W1 0 1 A0 r R1B W2 0 1 A0 r R1C W3 0 1 A0 r R1D 1 A8 d R1E pE 2 50 W6 3 0 W3 W4 W2 0 C13 W0 3 0 W1 0 1 A0 r R1B W2 0 1 A0 r R1C W3 0 1 A0 r R1D 1 A8 d R1E nE 2 20