[Cyan]<DATools6.0>EU2>EU2Sim.mesa!2

EU2Sim.mesa

Created by Bertrand Serlet July 31, 1985 3:03:17 pm PDT

Last edited by Bertrand Serlet June 8, 1986 5:21:11 pm PDT

Barth, April 16, 1986 3:05:40 pm PST

Louis Monier June 14, 1986 10:50:12 pm PDT

DIRECTORY

Core, CoreClasses, CoreCreate, CoreOps, CoreProperties, EU2Utils, Rope, Rosemary, RosemaryUser, Ports;

EU2Sim: CEDAR PROGRAM

IMPORTS EU2Utils, Rosemary, RosemaryUser, Ports =

BEGIN OPEN Core, EU2Utils;

Test of EU2

Vdd, Gnd, PadVdd, PadGnd, PhA, PhB, VRef,

DPRejectB, DPData, -- 32 bits

KBus, -- 32 bits

-- Phase-multiplexed on KBus

aAdr [0..7]

bAdr [8..15]

cAdr [16..23]

EUSt3AisCBus2BA [24]

EUAluLeftSrc1BA [25..26]

EUAluRightSrc1BA [27..29]

EUStore2ASrc1BA [30..31]

EURes3BisPBus3AB, EUWriteToPBus3AB,

EUAluOp2AB, -- 4 bits Dragon.ALUOps

EUCondSel2AB, -- 4 bits Dragon.CondSelects

EUCondition2B,

DShA, DShB, DShRd, DShWt, DShIn, DShOut, DHold, DStAd: NAT;

testName: ROPE = "EU2Test";

ExerciseRose: PUBLIC PROC [eu2: CellType] RETURNS [sim: Rosemary.Simulation] = {

public: Wire ← eu2.public;

Vdd ← PortIndex[public, "Vdd"];

Gnd ← PortIndex[public, "Gnd"];

PadVdd ← PortIndex[public, "PadVdd"];

PadGnd ← PortIndex[public, "PadGnd"];

PhA ← PortIndex[public, "PhA"];

PhB ← PortIndex[public, "PhB"];

VRef ← PortIndex[public, "VRef"];

DPRejectB ← PortIndex[public, "DPRejectB"];

DPData ← PortIndex[public, "DPData"];

KBus ← PortIndex[public, "KBus"];

EURes3BisPBus3AB ← PortIndex[public, "EURes3BisPBus3AB"];

EUWriteToPBus3AB ← PortIndex[public, "EUWriteToPBus3AB"];

EUAluOp2AB ← PortIndex[public, "EUAluOp2AB"];

EUCondSel2AB ← PortIndex[public, "EUCondSel2AB"];

EUCondition2B ← PortIndex[public, "EUCondition2B"];

DShA ← PortIndex[public, "DShA"];

DShB ← PortIndex[public, "DShB"];

DShRd ← PortIndex[public, "DShRd"];

DShWt ← PortIndex[public, "DShWt"];

DShIn ← PortIndex[public, "DShIn"];

DShOut ← PortIndex[public, "DShOut"];

DHold ← PortIndex[public, "DHold"];

DStAd ← PortIndex[public, "DStAd"];

[] ← Rosemary.SetFixedWire[public[Vdd], H];

[] ← Rosemary.SetFixedWire[public[Gnd], L];

[] ← Rosemary.SetFixedWire[public[PadVdd], H];

[] ← Rosemary.SetFixedWire[public[PadGnd], L];

[] ← Rosemary.SetFixedWire[public[VRef], H];

[] ← Ports.InitTesterDrive[public[PhA], force];

[] ← Ports.InitTesterDrive[public[PhB], force];

[] ← Ports.InitTesterDrive[public[DPRejectB], force];

[] ← Ports.InitPort[public[DPData], lc];

[] ← Ports.InitTesterDrive[public[DPData], expect];

[] ← Ports.InitPort[public[KBus], lc];

[] ← Ports.InitTesterDrive[public[KBus], force];

[] ← Ports.InitTesterDrive[public[EURes3BisPBus3AB], force];

[] ← Ports.InitTesterDrive[public[EUWriteToPBus3AB], force];

[] ← Ports.InitPort[public[EUAluOp2AB], c];

[] ← Ports.InitTesterDrive[public[EUAluOp2AB], force];

[] ← Ports.InitPort[public[EUCondSel2AB], c];

[] ← Ports.InitTesterDrive[public[EUCondSel2AB], force];

[] ← Ports.InitTesterDrive[public[EUCondition2B], expect];

[] ← Ports.InitTesterDrive[public[DShA], force];

[] ← Ports.InitTesterDrive[public[DShB], force];

[] ← Ports.InitTesterDrive[public[DShRd], force];

[] ← Ports.InitTesterDrive[public[DShWt], force];

[] ← Ports.InitTesterDrive[public[DShIn], force];

[] ← Ports.InitTesterDrive[public[DShOut], none];

[] ← Ports.InitTesterDrive[public[DHold], force];

[] ← Ports.InitPort[public[DStAd], c];

[] ← Ports.InitTesterDrive[public[DStAd], force];

sim ← RosemaryUser.TestProcedureViewer[

cellType: eu2,

testButtons: LIST[testName],

name: testName,

displayWires: RosemaryUser.DisplayCellTypePortLeafWires[eu2],

flatten: TRUE,

cutSets: LIST["AlpsCell", "EU2Ram"]];

};

EU2Test: RosemaryUser.TestProc = {

constAdr: NAT ← EU2Utils.constAdr;

junkAdr: NAT ← EU2Utils.junkAdr;

PackK: PROC [a, b: NAT ← constAdr,

c: NAT ← junkAdr,

st3AisC: BOOL ← FALSE,

aluL, aluR, st2A: NAT ← 0] RETURNS [k: LONG CARDINAL] ~ {

k ← (((((LONG[a]*256+LONG[b])*256+LONG[c])*2+(IF st3AisC THEN 1 ELSE 0))*4+aluL)*8+aluR)*4+st2A;

};

Phase: TYPE = {A, B};

DoPh: PROC [ph: Phase] = {

p[PhA].b ← ph=A;

p[PhB].b ← ph=B;

Eval[];

p[PhA].b ← FALSE;

p[PhB].b ← FALSE;

Eval[];

};

p[DPRejectB].b ← FALSE;

p[KBus].lc ← PackK[c: 1]; -- aAdr=bAdr=Const0, cAdr=1, everything else =0

p[EURes3BisPBus3AB].b ← FALSE; -- (fetch) read data from PBus

p[EUWriteToPBus3AB].b ← TRUE; -- (store) but don't write onto PBus during PhB

p[EUAluOp2AB].c ← 0; -- OR

p[EUCondSel2AB].c ← 0; -- false

p[DShA].b ← TRUE; -- hack to clean up the ShReg.

p[DShB].b ← TRUE;

p[DShRd].b ← FALSE;

p[DShWt].b ← FALSE;

p[DShIn].b ← FALSE;

p[DHold].b ← FALSE;

p[DStAd].c ← 0;

p[DPData].d ← none;

FOR c: NAT IN [0..4) DO

DoPh[B ! Rosemary.Stop => RESUME];

DoPh[A ! Rosemary.Stop => RESUME];

ENDLOOP;

-- Test starts here

-- read two zeros out of the RAM, OR them, send this on PBus (PhA) and write in RAM[1]

-- check the PBus

FOR cyles: INT IN [0..10) DO

p[DPData].d ← expect;

p[DPData].lc ← 0;

DoPh[A];

p[DPData].d ← none;

DoPh[B];

ENDLOOP;

};

RosemaryUser.RegisterTestProc[testName, EU2Test];

END.