<> <> <> <<>> DIRECTORY Core, EU2Utils, Ports; <<>> EU2Ram: CEDAR DEFINITIONS = BEGIN Vdd, Gnd, dRamRead, nPrech, selA, selB, selC, selALow, selBLow, selCLow: NAT; ramA, ramB, cBus: NAT; <<-- (ramA, ramB, cBus)[0..32)>> <<-- (selA, selB, selC)[0..nRows), (selALow, selBLow, selCLow)[0..4), Vdd, Gnd, dRamRead, nPrech>> CreateEU2Ram: PROC RETURNS [Core.CellType]; EU2RamState: TYPE = REF EU2RamStateRec; EU2RamStateRec: TYPE = RECORD[ ram: SEQUENCE size: NAT OF Ports.LevelSequence]; END.