[Cyan]<DATools6.0>EU2>EU2InnerImpl.mesa!2

EU2InnerImpl.mesa

Louis Monier June 14, 1986 5:21:09 pm PDT

Bertrand Serlet June 7, 1986 7:34:12 pm PDT

DIRECTORY Core, CoreCreate, CoreOps, EU2Inner, EU2ControlAlps, EU2LeafUtils, EU2Utils, LayoutCheckpoint, PWCore, PWCoreRoute;

EU2InnerImpl: CEDAR PROGRAM

IMPORTS CoreCreate, CoreOps, EU2ControlAlps, EU2LeafUtils, EU2Utils, LayoutCheckpoint, PWCore, PWCoreRoute

EXPORTS EU2Inner =

BEGIN OPEN EU2Inner, EU2Utils, CoreCreate;

CreateEU2Inner: PUBLIC PROC RETURNS [cellType: CellType] = {

channelData: PWCoreRoute.ChannelData;

public: Wire ← Union[GenPGnEWires[], GenWiresForOnion[], Wires["VRef"]];

Vdd: Wire ← FindWire[public, "Vdd"];

Gnd: Wire ← FindWire[public, "Gnd"];

phA: Wire ← FindWire[public, "phA"];

phB: Wire ← FindWire[public, "phB"];

nPhA: Wire ← FindWire[public, "nPhA"];

nPhB: Wire ← FindWire[public, "nPhB"];

VRef: Wire ← FindWire[public, "VRef"];

enWrtIFUPhA: Wire ← FindWire[public, "enWrtIFUPhA"];

enWrtIFUPhB: Wire ← FindWire[public, "enWrtIFUPhB"];

enWrtPBusPhA: Wire ← FindWire[public, "enWrtPBusPhA"];

enWrtPBusPhB: Wire ← FindWire[public, "enWrtPBusPhB"];

write: Wire ← FindWire[public, "write"];

read: Wire ← FindWire[public, "read"];

hold: Wire ← FindWire[public, "hold"];

dStateAd: Wire ← FindWire[public, "dStateAd"];

onlyInternal, kReg, ramAdr, ctrl8, partOfInternal: Wire;

dp, ctrl: CellType;

IF EU2Utils.useInnerCheckpoint THEN RETURN [LayoutCheckpoint.Retrieve["EU2Inner"]];

PrintStart["Inner"];

dp ← IF EU2Utils.useDataPathCheckpoint

THEN LayoutCheckpoint.Retrieve["EU2DataPath"]

ELSE EU2LeafUtils.Extract["EU2DataPath.sch"];

ctrl ← EU2ControlAlps.CreateControl[];

-- internal

partOfInternal ← GenWiresForRouter[];

kReg ← FindWire[partOfInternal, "kReg"];

ramAdr ← TransferStructure[FindWire[ctrl.public, "ramAdr"], Range[kReg, 0, 24]];

ctrl8 ← TransferStructure[FindWire[ctrl.public, "ctrl8"], Range[kReg, 24, 8]];

onlyInternal ← Union[partOfInternal, Wires[ramAdr, ctrl8]];

channelData ← NEW[PWCoreRoute.ChannelDataRec ← [

inX: TRUE,

bottomOrLeftWires: LIST[Vdd, Gnd, phA, phB, nPhA, nPhB, enWrtPBusPhA, enWrtPBusPhB],

topOrRightWires: LIST[Vdd, Gnd, enWrtIFUPhA, enWrtIFUPhB, write, read, hold, dStateAd],

trunkLayer: "metal2",

branchLayer: "metal",

extend: TRUE,

extendTopOrRight: FALSE,

wireWidthProc: PWCoreRoute.GndAndVdd25Met2MinWidth

]];

cellType ← Cell[

name: "EU2Inner",

public: public,

onlyInternal: onlyInternal,

instances: LIST [

Instance[ctrl,

["ramAdr", ramAdr], ["ctrl8", ctrl8],

["carryBAIn", "carryBA"], ["carryABIn", "carryAB"], ["conditionIn", "condition"]

Instance[dp] ]

];

PWCore.SetLayout[cellType, $Channel, $ChannelData, channelData];

PrintStop["Inner"];

};

-- internal is flat, and #atomic[public]=#atomic[internal]

TransferStructure: PROC [public, internal: Wire] RETURNS [actual: Wire] = {

iPos: NAT ← 0;

LeftToRightInWire: PROC [public: Wire] RETURNS [actual: Wire] = {

IF public.size=0 THEN {

actual ← internal[iPos];

iPos ← iPos + 1;

}

ELSE {

actual ← CoreOps.CreateWires[size: public.size];

FOR subWire: NAT IN [0..public.size) DO

actual[subWire] ← LeftToRightInWire[public[subWire]];

ENDLOOP;

};

actual ← LeftToRightInWire[public];

IF internal.size#iPos THEN ERROR;

};

END.