<> <> <> DIRECTORY Asserting, HashTable, IO, Rope; Core2: CEDAR DEFINITIONS = BEGIN <> <> <> LORA: TYPE = LIST OF REF ANY; ROPE: TYPE = Rope.ROPE; RopeList: TYPE = LIST OF ROPE; SymbolTable: TYPE = HashTable.Table; Assertions: TYPE = Asserting.Assertions; <> <> Vertex: TYPE = REF VertexPrivate; VertexPrivate: TYPE = RECORD [ firstEdge, lastEdge: Edge _ NIL, extraConnections: SymbolTable _ NIL, names: RopeList _ NIL, container: CellType, other: Assertions _ NIL, variant: SELECT class: VertexClass FROM wire => [ parent: Wire _ NIL, myIndex: NAT _ 0, elts: SEQUENCE length: NAT OF Wire ], cell => [ type: CellType _ NIL, nextInstance, prevInstance: Vertex _ NIL ], ENDCASE ]; VertexClass: TYPE = {wire, cell}; Wire: TYPE = REF WirePrivate; WirePrivate: TYPE = VertexPrivate[wire]; CellInstance: TYPE = REF CellInstancePrivate; CellInstancePrivate: TYPE = VertexPrivate[cell]; Edge: TYPE = REF EdgePrivate; EdgePrivate: TYPE = RECORD [ sides: ARRAY VertexClass OF RECORD [v: Vertex, next, prev: Edge], other: Assertions _ NIL, portIndex: CARDINAL]; <> CellType: TYPE = REF CellTypePrivate; CellTypePrivate: TYPE = RECORD [ names: RopeList _ NIL, ports: PortS _ NIL, <> <> parts: SymbolTable _ NIL, mirror: Vertex _ NIL, --the outside world, as seen from the inside <> <> asArray: Array _ NIL, wireCount, cellCount: NAT _ 0, <> firstInstance, lastInstance: Vertex _ NIL, otherPublic, otherPrivate: Assertions _ NIL]; <> <> PortS: TYPE = REF PortSeq; PortSeq: TYPE = RECORD [ports: SEQUENCE length: PortIndex OF Port]; PortIndex: TYPE = NAT; NullPortIndex: PortIndex = LAST[PortIndex]; Port: TYPE = RECORD [ names: RopeList _ NIL, netNames: RopeList _ NIL, <> other: Assertions _ NIL]; <> <> <> <> <> Array: TYPE = REF ArrayPrivate; ArrayPrivate: TYPE = RECORD [ eltType: CellType, shape: ARRAY Dim OF Range, joints: ARRAY Dim--perp to joint-- OF ARRAY Phase--perp to dim-- OF ARRAY Phase--along dim-- OF Joint _ ALL[ALL[ALL[NIL]]], portConnections: ArrayPortConnections, <> porting: SEQUENCE eltPorts: PortIndex OF Porting <> ]; Dim--ension--: TYPE = {Foo, Bar}; OtherDim: ARRAY Dim OF Dim = [Foo: Bar, Bar: Foo]; Range: TYPE = RECORD [min, maxPlusOne: INT]; Phase: TYPE = INTEGER [0 .. MaxPeriod); MaxPeriod: INTEGER = 2; Joint: TYPE = REF JointSeq; JointSeq: TYPE = RECORD [joints: SEQUENCE eltPorts: PortIndex OF RECORD [low, high: PortIndex]]; <> <> Porting: TYPE = REF ANY --actually UNION [{notPorted, unknownPorting}, DetailedPorting]--; notPorted: Porting; unknownPorting: Porting; DetailedPorting: TYPE = REF DetailedPortingRep; DetailedPortingRep: TYPE = RECORD [ corners: ARRAY End--Foo-- OF ARRAY End--Bar-- OF PortIndex, <> <> sideIndices: ARRAY End OF ARRAY Dim OF SideIndex, <> slots: SEQUENCE length: NAT OF PortIndex]; End: TYPE = {low, high}; OtherEnd: ARRAY End OF End = [low: high, high: low]; SideIndex: TYPE = RECORD [same: BOOL, firstSlot: NAT]; ArrayPortConnections: TYPE = REF ArrayPortConnectionSeq; ArrayPortConnectionSeq: TYPE = RECORD [SEQUENCE arrayPorts: PortIndex OF ARRAY End OF ARRAY Dim OF SideConnection]; SideConnection: TYPE = RECORD [range: Range, sockets: ArraySocketList]; ArraySocketList: TYPE = LIST OF ArraySocket; ArraySocket: TYPE = RECORD [ai: ArrayIndex, pi: PortIndex]; ArrayIndex: TYPE = ARRAY Dim OF INT; END.