DIRECTORY Core; NewCoreClasses: CEDAR DEFINITIONS = BEGIN OPEN Core; Volts: TYPE = REAL; KOhms: TYPE = REAL; pF: TYPE = REAL; ns: TYPE = REAL; mA: TYPE = REAL; uH: TYPE = REAL; RopeFromVolts: PROC [v: Volts] RETURNS [rope: ROPE]; RopeFromKOhms: PROC [r: KOhms] RETURNS [rope: ROPE]; RopeFrompF: PROC [c: pF] RETURNS [rope: ROPE]; RopeFromns: PROC [t: ns] RETURNS [rope: ROPE]; RopeFrommA: PROC [i: mA] RETURNS [rope: ROPE]; RopeFromuH: PROC [l: uH] RETURNS [rope: ROPE]; resistorCellClass: CellClass; Resistor: TYPE = REF ResistorRec; ResistorRec: TYPE = RECORD [ value: KOhms]; ResistorPort: TYPE = MACHINE DEPENDENT {n0(0), n1(1)}; CreateResistor: PROC [args: ResistorRec, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [resistor: CellType]; inductorCellClass: CellClass; Inductor: TYPE = REF InductorRec; InductorRec: TYPE = RECORD [ value: uH]; InductorPort: TYPE = MACHINE DEPENDENT {n0(0), n1(1)}; CreateInductor: PROC [args: InductorRec, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [inductor: CellType]; capacitorCellClass: CellClass; Capacitor: TYPE = REF CapacitorRec; CapacitorRec: TYPE = RECORD [ value: pF]; CapacitorPort: TYPE = MACHINE DEPENDENT {n0(0), n1(1)}; CreateCapacitor: PROC [args: CapacitorRec, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [capacitor: CellType]; signalGeneratorCellClass: CellClass; SignalGenerator: TYPE = REF SignalGeneratorRec; SignalGeneratorRec: TYPE = RECORD [ type: SignalGeneratorType _ DC, onLevel: Volts _ 5.0, offLevel: Volts _ 0.0, period: ns _ 0.0, width: ns _ 0.0, tRise: ns _ 0.0, tFall: ns _ 0.0, tDelay: ns _ 0.0]; SignalGeneratorType: TYPE = {DC, RectWave, OneShot, Step}; SignalGeneratorPort: TYPE = MACHINE DEPENDENT {n(0)}; CreateSignalGenerator: PROC [args: SignalGeneratorRec, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [signalGenerator: CellType]; probeCellClass: CellClass; Probe: TYPE = REF ProbeRec; ProbeRec: TYPE = RECORD [ type: ProbeType _ Voltage, scale: REAL _ 1.0, resistance: KOhms _ 0.001]; ProbeType: TYPE = {Voltage, Current}; CreateProbe: PROC [args: ProbeRec, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [probe: CellType]; initCellClass: CellClass; Init: TYPE = REF InitRec; InitRec: TYPE = RECORD [ type: InitType _ Voltage, value: REAL _ 5.0, time: ns _ 0.0]; InitType: TYPE = {Voltage, Current}; CreateInit: PROC [args: InitRec, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [init: CellType]; thymePanelCellClass: CellClass; ThymePanel: TYPE = REF ThymePanelRec; ThymePanelRec: TYPE = RECORD [ title: ROPE _ NIL, tMin: ns _ 0.0, tMax: ns _ 100.0, yMin: Volts _ -1.0, yMax: Volts _ 5.0, tScale: REAL _ 1.0, iScale: mA _ 1.0]; CreateThymePanel: PROC [args: ThymePanelRec, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [thymePanel: CellType]; END. ²NewCoreClasses.mesa Written by: Pradeep Sindhu April 1, 1986 1:12:34 am PST Last Edited by: Pradeep Sindhu April 30, 1986 10:31:53 pm PDT Basic Types and Associated Procs Resistor Public wires: n1, n2. Inductor Public wires: n1, n2. Capacitor Public wires: n1, n2. SignalGenerator Public wires: n. Probe Public wires: depends on the type of probe. Init Public wires: depends on the type of init. ThymePanel Public wires: none. ΚΔ˜™Icode™7™K™-——J™šΟk ˜ K˜K˜—Jš Πblœœ œœœ˜4head™ Kšœœœ˜Kšœœœ˜Kšœœœ˜Kšœœœ˜Kšœœœ˜Kšœœœ˜K˜KšΟn œœ œœ˜4KšŸ œœ œœ˜4KšŸ œœ œœ˜.KšŸ œœ œœ˜.KšŸ œœ œœ˜.Kš ΠbnΟbœœ œœ˜.—™K˜Kšœ œœ ˜!šœ œœ˜Kšœ˜K˜—šœœœ œ˜6K˜—Jšœ™Kš Ÿœœœœœœ˜q—™K˜Kšœ œœ ˜!šœ œœ˜Kšœ ˜ K˜—šœœœ œ˜6K˜—Jšœ™Kš Ÿœœœœœœ˜q—™ K˜Kšœ œœ˜#šœœœ˜Kšœ ˜ K˜—šœœœ œ˜7K˜—Jšœ™Kš Ÿœœœœœœ˜t—™K˜$Kšœœœ˜/šœœœ˜#Kšœœ˜Kšœ˜Kšœ˜Kšœ˜Kšœ˜Kšœ˜Kšœ˜Kšœ˜K˜—Kšœœœ˜:K˜šœœœ œ˜5K˜—Jšœ™Kš Ÿœœ"œœœœ˜†J˜—™K˜Kšœœœ ˜šœ œœ˜Kšœ˜Kšœœ˜Kšœ˜K˜—Kšœ œ˜%K˜Jšœ+™+Kš Ÿ œœœœœœ˜hJ˜—™K˜Kšœœœ ˜šœ œœ˜Kšœ˜Kšœœ˜Kšœ˜K˜—Kšœ œ˜$K˜Jšœ*™*Kš Ÿ œœœœœœ˜eJ˜—™ K˜Kšœ œœ˜%šœœœ˜Jšœœœ˜Jšœ˜Jšœ˜Jšœ˜Jšœ˜Kšœœ˜Kšœ˜K˜—Jšœ™Kš Ÿœœœœœœ˜wJ˜—Jšœ˜K˜J˜—…— κ`