DIRECTORY
CommandTool, Convert, CoreOps, CoreClasses, CoreProperties, CoreThyme, HashTable, NewCoreClasses, Rope, spGlobals, TerminalIO, TiogaFileOps, ViewerTools;

CoreThymeImpl: CEDAR PROGRAM				
IMPORTS Convert, CoreOps, CoreClasses, CoreProperties, HashTable, NewCoreClasses, Rope, spGlobals, TerminalIO, TiogaFileOps, ViewerTools
EXPORTS CoreThyme =
BEGIN OPEN CoreThyme;

TNode: TYPE = TiogaFileOps.Ref;
WireFilterProc: TYPE = PROC [wire: Wire] RETURNS [BOOL];

wId, cId, iId: INT _ 0;	-- Used in naming unnamed wires, cells and instances
isPublic: ATOM _ CoreProperties.RegisterProperty[$CoreThymeIsPublic, CoreProperties.Props[[CoreProperties.propCopy, CoreProperties.PropDoCopy]]];
pathNameProp: ATOM _ CoreProperties.RegisterProperty[$CoreThymePathName, CoreProperties.Props[[CoreProperties.propCopy, CoreProperties.PropDoCopy]]];
probeWireProp: ATOM _ CoreProperties.RegisterProperty[$CoreThymeProbeWire, CoreProperties.Props[[CoreProperties.propCopy, CoreProperties.PropDoCopy]]];
alreadyNamedProp: ATOM _ CoreProperties.RegisterProperty[$CoreThymeAlreadyNamed, CoreProperties.Props[[CoreProperties.propCopy, CoreProperties.PropDoCopy]]];

CreateThymeViewer: PUBLIC PROC [wDir: ROPE] RETURNS [handle: ThymeHandle] = BEGIN
handle _ spGlobals.MakeThymeViewers[wDir];
END;

SetWorkingDirectory: PUBLIC PROC [wDir: ROPE, handle: ThymeHandle] = BEGIN
spGlobals.SetWorkingDirectory[wDir, handle];
END;


Translate: PUBLIC PROC [cellType: CellType, outputFile: ROPE] = BEGIN
root: TNode;

wId _ 0; cId _ 0; iId _ 0;
root _ TiogaFileOps.CreateRoot[];
PutHeader[outputFile, root];
PutTopLevelCircuit[cellType, root];
TiogaFileOps.Store[root, outputFile]
END;


Simulate: PUBLIC PROC  [inputFile: ROPE, handle: ThymeHandle] = BEGIN
ViewerTools.SetContents[handle.input, inputFile];
spGlobals.NormalRun[handle];
END;

PutHeader: PROC  [outputFile: ROPE, root: TNode] = BEGIN
node: TNode;

TiogaFileOps.SetStyle[root, "Cedar"];
node _ TiogaFileOps.InsertAsLastChild[root];
TiogaFileOps.SetContents[node, Rope.Cat["-- ", outputFile]];
[] _ TiogaFileOps.InsertAsLastChild[root];
END;


PutTopLevelCircuit: PROC [cellType: CellType, root: TNode] = BEGIN
tNode: TNode _ TiogaFileOps.InsertAsLastChild[root];
tSubNode: TNode;
plotSpec, initSpec: ROPE;
resultList: LIST OF CellInstance;
thymePanelCT: CellType;
thymePanel: NewCoreClasses.ThymePanel;

IF cellType.class#CoreClasses.recordCellClass THEN ERROR;
TiogaFileOps.SetContents[tNode, "CIRCUIT[Lambda _ 1, TDegC _ 25] = {"];
tSubNode _ TiogaFileOps.InsertAsLastChild[tNode];
TiogaFileOps.SetContents[tSubNode, "Vdd: Node;"];
tSubNode _ TiogaFileOps.InsertAsLastChild[tNode];
TiogaFileOps.SetContents[tSubNode, "! /DATools/DATools6.0/Thyme/SignalGenerators"];
tSubNode _ TiogaFileOps.InsertAsLastChild[tNode];
TiogaFileOps.SetContents[tSubNode, "! /DATools/DATools6.0/Thyme/BSIM"];
tSubNode _ TiogaFileOps.InsertAsLastChild[tNode];
TiogaFileOps.SetContents[tSubNode, "powerSupply: voltage[Vdd, Gnd] = 5.0;"];
[resultList, thymePanelCT] _ PutRecordCellType[cellType, root, TRUE];
IF thymePanelCT=NIL
THEN {TerminalIO.WriteRope["** Error: Sorry, no ThymePanel in cell\n"]; RETURN};
thymePanel _ NARROW[thymePanelCT.data, NewCoreClasses.ThymePanel];

FOR l: LIST OF CellInstance _ resultList, l.rest WHILE l#NIL DO
IF l.first.type.class=NewCoreClasses.initCellClass THEN {
init: NewCoreClasses.Init _ NARROW[l.first.type.data];
pathName: ROPE _ NARROW[CoreProperties.GetCellInstanceProp[l.first, pathNameProp]];
SELECT init.type FROM
Voltage => initSpec _ Rope.Cat[
Rope.Cat["IC[", NewCoreClasses.RopeFromns[init.time]],
", Vdd_ 5.0",
Rope.Cat[", ", pathName],
Rope.Cat["_ ", Convert.RopeFromReal[init.value], "];"]];
Current => ERROR; -- No Init Current for the moment
ENDCASE => ERROR;
tNode _ TiogaFileOps.InsertAsLastChild[root];
TiogaFileOps.SetContents[tNode, initSpec];
};
ENDLOOP;

tNode _ TiogaFileOps.InsertAsLastChild[root];
plotSpec _ Rope.Cat[
Rope.Cat["Plot[\"", thymePanel.title, "\", "],
Rope.Cat[":", NewCoreClasses.RopeFromns[thymePanel.tScale], ", "],
Rope.Cat[Convert.RopeFromReal[thymePanel.yMin], ", "],
Rope.Cat[Convert.RopeFromReal[thymePanel.yMax], ", "],
Rope.Cat["powerSupply^: ", NewCoreClasses.RopeFrommA[thymePanel.iScale]]];

FOR l: LIST OF CellInstance _ resultList, l.rest WHILE l#NIL DO
IF l.first.type.class=NewCoreClasses.probeCellClass THEN {
probe: NewCoreClasses.Probe _ NARROW[l.first.type.data];
pathName: ROPE _ NARROW[CoreProperties.GetCellInstanceProp[l.first, pathNameProp]];
SELECT probe.type FROM
Voltage => plotSpec _ Rope.Cat[plotSpec, ", ", pathName, ": ", Convert.RopeFromReal[probe.scale]];
Current => plotSpec _ Rope.Cat[plotSpec, ", ", pathName, "^: ", NewCoreClasses.RopeFrommA[probe.scale]];
ENDCASE => ERROR;
};
ENDLOOP;
plotSpec _ Rope.Cat[plotSpec, "];"];
TiogaFileOps.SetContents[tNode, plotSpec];

tNode _ TiogaFileOps.InsertAsLastChild[root];
TiogaFileOps.SetContents[tNode, Rope.Cat["Run[",
Rope.Cat["tMin _ ", NewCoreClasses.RopeFromns[thymePanel.tMin], ", "],
Rope.Cat["tMax _ ", NewCoreClasses.RopeFromns[thymePanel.tMax], "];"]
]];
END;


WireToAtomicWires: PROC [wire: Wire] RETURNS [wires: Wires] = BEGIN
AddToWires: PROC [subWire: Wire] = {
wires _ CONS[subWire, wires];
};
wires _ NIL;
CoreOps.VisitAtomicWires[wire, AddToWires];
wires _ CoreOps.Reverse[wires]
END;

Filter: PROC [in: Wires, filter: WireFilterProc] RETURNS [out: Wires] = BEGIN
out _ NIL;
FOR l: Wires _ in, l.rest WHILE l#NIL DO
IF ~filter[l.first] THEN out _ CONS[l.first, out]
ENDLOOP;
out _ CoreOps.Reverse[out];
END; 

IsPublic: WireFilterProc = BEGIN
RETURN [CoreProperties.GetWireProp[wire, isPublic]#NIL]
END;

IsVddOrGnd: WireFilterProc = BEGIN
name: ROPE _ CoreOps.GetShortWireName[wire];
RETURN [Rope.Equal[name, "Vdd"] OR Rope.Equal[name, "Gnd"]];
END;

WiresToRope: PROC [root: Wire, wires: Wires] RETURNS [rope: ROPE] = BEGIN
separator: ROPE _ ", ";
rope _ NIL;
FOR l: Wires _ wires, l.rest WHILE l#NIL DO
rope _ Rope.Cat[rope, separator, CoreOps.GetFullWireName[root, l.first]]
ENDLOOP;
IF rope#NIL THEN rope _ Rope.Substr[rope, Rope.Length[separator], Rope.Length[rope]];
rope _ Rope.Translate[base: rope, translator: NameTranslator];
END;

ActualsToRope: PROC [public, internal: Wire, wires: Wires] RETURNS [rope: ROPE] = BEGIN
separator: ROPE _ ", ";
rope _ NIL;
FOR l: Wires _ wires, l.rest WHILE l#NIL DO
rope _ Rope.Cat[rope, separator, CoreOps.GetFullWireName[IF IsPublic[l.first] THEN public ELSE internal, l.first]]
ENDLOOP;
IF rope#NIL THEN rope _ Rope.Substr[rope, Rope.Length[separator], Rope.Length[rope]];
rope _ Rope.Translate[base: rope, translator: NameTranslator];
END;

NameTranslator: Rope.TranslatorType = BEGIN
SELECT old FROM
'* => new _ 'X;
'. => new _ 'x;
ENDCASE => new _ old;
END;

EnsureWireName: PROC [wire: Wire] RETURNS [name: ROPE] = BEGIN
name _ CoreOps.GetShortWireName[wire];
IF CoreProperties.GetWireProp[wire, alreadyNamedProp]#NIL THEN RETURN;
IF name=NIL
THEN {name _ Rope.Cat["Node", Convert.RopeFromInt[wId]]; wId _ wId+1}
ELSE name _ Rope.Translate[base: name, translator: NameTranslator];
[] _ CoreOps.SetShortWireName[wire, name];
CoreProperties.PutWireProp[wire, alreadyNamedProp, alreadyNamedProp];
END;


EnsureCTName: PROC [cellType: CellType] RETURNS [name: ROPE] = BEGIN
name _ CoreOps.GetCellTypeName[cellType];
IF CoreProperties.GetCellTypeProp[cellType, alreadyNamedProp]#NIL THEN RETURN;
IF name=NIL
THEN name _ Rope.Cat["Cell", Convert.RopeFromInt[cId]]
ELSE name _ Rope.Cat[Rope.Translate[base: name, translator: NameTranslator], Convert.RopeFromInt[cId]];
cId _ cId+1;
[] _ CoreOps.SetCellTypeName[cellType, name];
CoreProperties.PutCellTypeProp[cellType, alreadyNamedProp, alreadyNamedProp];
END;


EnsureInstName: PROC [inst: CellInstance] RETURNS [name: ROPE] = BEGIN
name _ CoreClasses.GetCellInstanceName[inst];
IF CoreProperties.GetCellInstanceProp[inst, alreadyNamedProp]#NIL THEN RETURN;
IF name=NIL
THEN {name _ Rope.Cat["Inst", Convert.RopeFromInt[iId]]; iId _ iId+1}
ELSE name _ Rope.Translate[base: name, translator: NameTranslator];
[] _ CoreClasses.SetCellInstanceName[inst, name];
CoreProperties.PutCellInstanceProp[inst, alreadyNamedProp, alreadyNamedProp];
END;
PutRecordCellType: PROC [cellType: CellType, root: TNode, topLevel: BOOL] RETURNS [resultList: LIST OF CellInstance _ NIL, thymePanel: CellType _ NIL] = BEGIN
tNode, subTNode: TNode;
tNodeContents, subTNodeContents: ROPE;
recordCT: CoreClasses.RecordCellType _ NARROW[cellType.data];
subCellTypeTab: HashTable.Table _ HashTable.Create[];

EnsureInternalNames: CoreOps.EachWireProc = {
IF wire#recordCT.internal THEN [] _ EnsureWireName[wire]
};

MarkPublicWire: CoreOps.EachWireProc = {
[] _ CoreProperties.PutWireProp[wire, isPublic, isPublic]
};
[] _ CoreOps.VisitWire[recordCT.internal, EnsureInternalNames];
[] _ CoreOps.VisitWire[cellType.public, MarkPublicWire];
CoreOps.FlushNameCaches[recordCT.internal];
CoreOps.FlushNameCaches[cellType.public];
[] _ EnsureCTName[cellType];
tNode _ TiogaFileOps.InsertAsLastChild[root];
IF ~topLevel THEN {
tNodeContents _ Rope.Cat[
CoreOps.GetCellTypeName[cellType],
": CIRCUIT[",
WiresToRope[cellType.public, WireToAtomicWires[cellType.public]],
"] = {"
];
TiogaFileOps.SetContents[tNode, tNodeContents];
};

IF topLevel
THEN subTNodeContents _ WiresToRope[recordCT.internal, Filter[WireToAtomicWires[recordCT.internal], IsVddOrGnd]]
ELSE subTNodeContents _ WiresToRope[recordCT.internal, Filter[WireToAtomicWires[recordCT.internal], IsPublic]];
IF subTNodeContents#NIL AND ~Rope.Equal[subTNodeContents, ""] THEN {
subTNode _ TiogaFileOps.InsertAsLastChild[tNode];
TiogaFileOps.SetContents[subTNode, Rope.Cat[subTNodeContents, ": Node;"]]
};

FOR i: NAT IN [0..recordCT.size) DO
inst: CellInstance _ recordCT.instances[i];
WHILE inst.type.class=CoreClasses.identityCellClass DO
inst.type _ CoreOps.Recast[inst.type];
ENDLOOP;

SELECT inst.type.class FROM
CoreClasses.recordCellClass => {
instName: ROPE _ EnsureInstName[inst];
found: BOOL;
value: HashTable.Value;
subCellTypeResultList: LIST OF CellInstance;

[found, value] _ HashTable.Fetch[subCellTypeTab, inst.type];
IF found
THEN subCellTypeResultList _ NARROW[value, LIST OF CellInstance]
ELSE {
subCellTypeResultList _ PutRecordCellType[inst.type, tNode, FALSE].resultList;
[] _ HashTable.Insert[subCellTypeTab, inst.type, subCellTypeResultList]};
subTNode _ TiogaFileOps.InsertAsLastChild[tNode];
subTNodeContents _ Rope.Cat[
Rope.Cat[instName, ": ", CoreOps.GetCellTypeName[inst.type]],
"[",
ActualsToRope[cellType.public, recordCT.internal, WireToAtomicWires[inst.actual]],
"];"];
TiogaFileOps.SetContents[subTNode, subTNodeContents];

FOR l: LIST OF CellInstance _ subCellTypeResultList, l.rest WHILE l#NIL DO
pathName: ROPE _ NARROW[CoreProperties.GetCellInstanceProp[l.first, pathNameProp]];
voltageProbeOnPublicWire: BOOL _ FALSE;

IF l.first.type.class=NewCoreClasses.probeCellClass THEN {
probe: NewCoreClasses.Probe _ NARROW[l.first.type.data];
IF probe.type=Voltage THEN {
probeWire: Wire _ NARROW[CoreProperties.GetCellInstanceProp[l.first, probeWireProp]];
ForEachBinding: CoreOps.EachWirePairProc = {
IF publicWire=probeWire THEN {
voltageProbeOnPublicWire _ TRUE;
pathName _ WiresToRope[recordCT.internal, WireToAtomicWires[actualWire]];
CoreProperties.PutCellInstanceProp[l.first, probeWireProp, actualWire];
};
};
[] _ CoreOps.VisitBinding[inst.actual, inst.type.public, ForEachBinding]
};
};
IF ~voltageProbeOnPublicWire THEN pathName _ Rope.Cat[instName, "/", pathName];
[] _ CoreProperties.PutCellInstanceProp[l.first, pathNameProp, pathName];
resultList _ CONS[l.first, resultList];
ENDLOOP;
};
CoreClasses.transistorCellClass =>
PutTransistorInstance[recordCT.internal, inst, tNode];
NewCoreClasses.resistorCellClass =>
PutResistorInstance[recordCT.internal, inst, tNode];
NewCoreClasses.inductorCellClass =>
PutInductorInstance[recordCT.internal, inst, tNode];
NewCoreClasses.capacitorCellClass =>
PutCapacitorInstance[recordCT.internal, inst, tNode];
NewCoreClasses.signalGeneratorCellClass =>
PutSignalGeneratorInstance[recordCT.internal, inst, tNode];
NewCoreClasses.probeCellClass => {
probe: NewCoreClasses.Probe _ NARROW[inst.type.data];
SELECT probe.type FROM
Voltage => {
[] _ CoreProperties.PutCellInstanceProp[inst, pathNameProp, WiresToRope[recordCT.internal, WireToAtomicWires[inst.actual]]];
[] _ CoreProperties.PutCellInstanceProp[inst, probeWireProp, inst.actual.elements[0]];
};
Current => {
useResistor: BOOL _ probe.resistance>0.001;
instName: ROPE _ EnsureInstName[inst];
[] _ CoreProperties.PutCellInstanceProp[inst, pathNameProp, instName];
subTNode _ TiogaFileOps.InsertAsLastChild[tNode];
subTNodeContents _ Rope.Cat[
Rope.Cat[instName, IF useResistor THEN ": Resistor[" ELSE ": Voltage["],
ActualsToRope[cellType.public, recordCT.internal, WireToAtomicWires[inst.actual]],
"] = ",
IF useResistor THEN NewCoreClasses.RopeFromKOhms[probe.resistance] ELSE NewCoreClasses.RopeFromVolts[0.0],
";"];
TiogaFileOps.SetContents[subTNode, subTNodeContents];
};
ENDCASE => ERROR;
resultList _ CONS[inst, resultList];
};
NewCoreClasses.initCellClass => {
init: NewCoreClasses.Init _ NARROW[inst.type.data];
SELECT init.type FROM
Voltage => [] _ CoreProperties.PutCellInstanceProp[inst, pathNameProp, WiresToRope[recordCT.internal, WireToAtomicWires[inst.actual]]];
Current => ERROR;
ENDCASE => ERROR;
resultList _ CONS[inst, resultList];
};
NewCoreClasses.thymePanelCellClass => thymePanel _ inst.type;
ENDCASE => ERROR;
ENDLOOP;

subTNode _ TiogaFileOps.InsertAsLastChild[tNode];
TiogaFileOps.SetContents[subTNode, "};"];
END;


PutTransistorInstance: PROC [rootWire: Wire, inst: CellInstance, rootTNode: TNode] = BEGIN
tNode: TNode;
tNodeContents: ROPE;
transistor: CoreClasses.Transistor _ NARROW[inst.type.data];
instName: ROPE _ EnsureInstName[inst];

tNode _ TiogaFileOps.InsertAsLastChild[rootTNode];
tNodeContents _ Rope.Cat[
Rope.Cat[instName, ": "],
SELECT transistor.type FROM
nE => "ETran",
pE => "CTran"
ENDCASE => ERROR,
Rope.Cat["[", WiresToRope[rootWire, WireToAtomicWires[inst.actual]], " | "],
Rope.Cat["L _ ", Convert.RopeFromInt[transistor.length], ", "],
Rope.Cat["W _ ", Convert.RopeFromInt[transistor.width], ", sdExtend _ 6];"]
];
TiogaFileOps.SetContents[tNode, tNodeContents];
END;

PutResistorInstance: PROC [rootWire: Wire, inst: CellInstance, rootTNode: TNode] = BEGIN
tNode: TNode;
tNodeContents: ROPE;
resistor: NewCoreClasses.Resistor _ NARROW[inst.type.data];
instName: ROPE _ EnsureInstName[inst];

tNode _ TiogaFileOps.InsertAsLastChild[rootTNode];
tNodeContents _ Rope.Cat[
Rope.Cat[instName, ": Resistor"],
Rope.Cat["[", WiresToRope[rootWire, WireToAtomicWires[inst.actual]], "] = "],
Rope.Cat[NewCoreClasses.RopeFromKOhms[resistor.value], ";"]
];
TiogaFileOps.SetContents[tNode, tNodeContents];
END;

PutInductorInstance: PROC [rootWire: Wire, inst: CellInstance, rootTNode: TNode] = BEGIN
tNode: TNode;
tNodeContents: ROPE;
inductor: NewCoreClasses.Inductor _ NARROW[inst.type.data];
instName: ROPE _ EnsureInstName[inst];

tNode _ TiogaFileOps.InsertAsLastChild[rootTNode];
tNodeContents _ Rope.Cat[
Rope.Cat[instName, ": Inductor"],
Rope.Cat["[", WiresToRope[rootWire, WireToAtomicWires[inst.actual]], "] = "],
Rope.Cat[NewCoreClasses.RopeFromuH[inductor.value], ";"]
];
TiogaFileOps.SetContents[tNode, tNodeContents];
END;

PutCapacitorInstance: PROC [rootWire: Wire, inst: CellInstance, rootTNode: TNode] = BEGIN
tNode: TNode;
tNodeContents: ROPE;
capacitor: NewCoreClasses.Capacitor _ NARROW[inst.type.data];
instName: ROPE _ EnsureInstName[inst];

tNode _ TiogaFileOps.InsertAsLastChild[rootTNode];
tNodeContents _ Rope.Cat[
Rope.Cat[instName, ": Capacitor"],
Rope.Cat["[", WiresToRope[rootWire, WireToAtomicWires[inst.actual]], "] = "],
Rope.Cat[NewCoreClasses.RopeFrompF[capacitor.value], ";"]
];
TiogaFileOps.SetContents[tNode, tNodeContents];
END;

PutSignalGeneratorInstance: PROC [rootWire: Wire, inst: CellInstance, rootTNode: TNode] = BEGIN
tNode: TNode;
tNodeContents: ROPE;
signalGenerator: NewCoreClasses.SignalGenerator _ NARROW[inst.type.data];
instName: ROPE _ EnsureInstName[inst];

tNode _ TiogaFileOps.InsertAsLastChild[rootTNode];
SELECT signalGenerator.type FROM
RectWave => {
tNodeContents _ Rope.Cat[
Rope.Cat[instName, ": RectWave"],
Rope.Cat[
Rope.Cat["[", WiresToRope[rootWire, WireToAtomicWires[inst.actual]], " | "],
Rope.Cat["OnLevel _ ", NewCoreClasses.RopeFromVolts[signalGenerator.onLevel], ", "],
Rope.Cat["OffLevel _ ", NewCoreClasses.RopeFromVolts[signalGenerator.offLevel], ", "],
Rope.Cat["period _ ", NewCoreClasses.RopeFromns[signalGenerator.period], ", "],
Rope.Cat["width _ ", NewCoreClasses.RopeFromns[signalGenerator.width], ", "]],
Rope.Cat[
Rope.Cat["tRise _ ", NewCoreClasses.RopeFromns[signalGenerator.tRise], ", "],
Rope.Cat["tFall _ ", NewCoreClasses.RopeFromns[signalGenerator.tFall], ", "],
Rope.Cat["tDelay _ ", NewCoreClasses.RopeFromns[signalGenerator.tDelay], "];"]]
];
};
OneShot => {
tNodeContents _ Rope.Cat[
Rope.Cat[instName, ": OneShot"],
Rope.Cat[
Rope.Cat["[", WiresToRope[rootWire, WireToAtomicWires[inst.actual]], " | "],
Rope.Cat["OnLevel _ ", NewCoreClasses.RopeFromVolts[signalGenerator.onLevel], ", "],
Rope.Cat["OffLevel _ ", NewCoreClasses.RopeFromVolts[signalGenerator.offLevel], ", "],
Rope.Cat["width _ ", NewCoreClasses.RopeFromns[signalGenerator.width], ", "]],
Rope.Cat[
Rope.Cat["tRise _ ", NewCoreClasses.RopeFromns[signalGenerator.tRise], ", "],
Rope.Cat["tFall _ ", NewCoreClasses.RopeFromns[signalGenerator.tFall], ", "],
Rope.Cat["tDelay _ ", NewCoreClasses.RopeFromns[signalGenerator.tDelay], "];"]]
];
};
Step => {
tNodeContents _ Rope.Cat[
Rope.Cat[instName, ": Step"],
Rope.Cat[
Rope.Cat["[", WiresToRope[rootWire, WireToAtomicWires[inst.actual]], " | "],
Rope.Cat["OnLevel _ ", NewCoreClasses.RopeFromVolts[signalGenerator.onLevel], ", "],
Rope.Cat["OffLevel _ ", NewCoreClasses.RopeFromVolts[signalGenerator.offLevel], ", "]],
Rope.Cat[
Rope.Cat["tRise _ ", NewCoreClasses.RopeFromns[signalGenerator.tRise], ", "],
Rope.Cat["tDelay _ ", NewCoreClasses.RopeFromns[signalGenerator.tDelay], "];"]]
];
};
DC => {
tNodeContents _ Rope.Cat[
Rope.Cat[instName, ": Voltage"],
Rope.Cat["[", WiresToRope[rootWire, WireToAtomicWires[inst.actual]], ", Gnd] = "],
Rope.Cat[NewCoreClasses.RopeFromVolts[signalGenerator.onLevel], ";"]
];
};
ENDCASE => ERROR;

TiogaFileOps.SetContents[tNode, tNodeContents];
END;

END.


δCoreThymeImpl.mesa
Written by: Pradeep Sindhu March 27, 1986 3:52:07 pm PST
Last Edited by:
Pradeep Sindhu May 6, 1986 11:32:01 am PDT
Christian Jacobi, June 11, 1986 4:01:24 pm PDT

Public Procs
Internal Procs
Put Init Specs
Put Plot Specs
Put Run Specs

Root is tioga node into which the recordCell definition will be inserted as a child

Ensure names on internal, mark public, and delete fullname caches

Put circuit header if needed
If top-level then put internal nodes except Vdd&Gnd else put internal minus public
Now put the instances
Put the definition if it isn't there already

Put the instance
Put the results in subCellTypeResultList onto resultList
Compute the replacementPathName if its a voltage probe on a public wire
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