NewCoreClasses.mesa
Written by: Pradeep Sindhu April 1, 1986 1:12:34 am PST
Last Edited by:
Pradeep Sindhu April 30, 1986 10:31:53 pm PDT
NewCoreClasses: CEDAR DEFINITIONS = BEGIN OPEN Core;
Basic Types and Associated Procs
Volts: TYPE = REAL;
KOhms: TYPE = REAL;
pF: TYPE = REAL;
ns: TYPE = REAL;
mA: TYPE = REAL;
uH: TYPE = REAL;
RopeFromVolts: PROC [v: Volts] RETURNS [rope: ROPE];
RopeFromKOhms: PROC [r: KOhms] RETURNS [rope: ROPE];
RopeFrompF: PROC [c: pF] RETURNS [rope: ROPE];
RopeFromns: PROC [t: ns] RETURNS [rope: ROPE];
RopeFrommA: PROC [i: mA] RETURNS [rope: ROPE];
RopeFromuH: PROC [l: uH] RETURNS [rope: ROPE];
Resistor
resistorCellClass: CellClass;
Resistor: TYPE = REF ResistorRec;
ResistorRec:
TYPE =
RECORD [
value: KOhms];
ResistorPort:
TYPE =
MACHINE
DEPENDENT {n0(0), n1(1)};
Public wires: n1, n2.
CreateResistor: PROC [args: ResistorRec, name: ROPE ← NIL, props: Properties ← NIL] RETURNS [resistor: CellType];
Inductor
inductorCellClass: CellClass;
Inductor: TYPE = REF InductorRec;
InductorRec:
TYPE =
RECORD [
value: uH];
InductorPort:
TYPE =
MACHINE
DEPENDENT {n0(0), n1(1)};
Public wires: n1, n2.
CreateInductor: PROC [args: InductorRec, name: ROPE ← NIL, props: Properties ← NIL] RETURNS [inductor: CellType];
Capacitor
capacitorCellClass: CellClass;
Capacitor: TYPE = REF CapacitorRec;
CapacitorRec:
TYPE =
RECORD [
value: pF];
CapacitorPort:
TYPE =
MACHINE
DEPENDENT {n0(0), n1(1)};
Public wires: n1, n2.
CreateCapacitor: PROC [args: CapacitorRec, name: ROPE ← NIL, props: Properties ← NIL] RETURNS [capacitor: CellType];
SignalGenerator
signalGeneratorCellClass: CellClass;
SignalGenerator: TYPE = REF SignalGeneratorRec;
SignalGeneratorRec:
TYPE =
RECORD [
type: SignalGeneratorType ← DC,
onLevel: Volts ← 5.0,
offLevel: Volts ← 0.0,
period: ns ← 0.0,
width: ns ← 0.0,
tRise: ns ← 0.0,
tFall: ns ← 0.0,
tDelay: ns ← 0.0];
SignalGeneratorType: TYPE = {DC, RectWave, OneShot, Step};
SignalGeneratorPort:
TYPE =
MACHINE
DEPENDENT {n(0)};
Public wires: n.
CreateSignalGenerator: PROC [args: SignalGeneratorRec, name: ROPE ← NIL, props: Properties ← NIL] RETURNS [signalGenerator: CellType];
Probe
probeCellClass: CellClass;
Probe: TYPE = REF ProbeRec;
ProbeRec:
TYPE =
RECORD [
type: ProbeType ← Voltage,
scale: REAL ← 1.0,
resistance: KOhms ← 0.001];
ProbeType: TYPE = {Voltage, Current};
Public wires: depends on the type of probe.
CreateProbe: PROC [args: ProbeRec, name: ROPE ← NIL, props: Properties ← NIL] RETURNS [probe: CellType];
Init
initCellClass: CellClass;
Init: TYPE = REF InitRec;
InitRec:
TYPE =
RECORD [
type: InitType ← Voltage,
value: REAL ← 5.0,
time: ns ← 0.0];
InitType: TYPE = {Voltage, Current};
Public wires: depends on the type of init.
CreateInit: PROC [args: InitRec, name: ROPE ← NIL, props: Properties ← NIL] RETURNS [init: CellType];
ThymePanel
thymePanelCellClass: CellClass;
ThymePanel: TYPE = REF ThymePanelRec;
ThymePanelRec:
TYPE =
RECORD [
title: ROPE ← NIL,
tMin: ns ← 0.0,
tMax: ns ← 100.0,
yMin: Volts ← -1.0,
yMax: Volts ← 5.0,
tScale: REAL ← 1.0,
iScale: mA ← 1.0];
Public wires: none.
CreateThymePanel: PROC [args: ThymePanelRec, name: ROPE ← NIL, props: Properties ← NIL] RETURNS [thymePanel: CellType];
END.