<> <> <> <> <> <> <<>> DIRECTORY Core, CoreClasses, CoreOps, CoreProperties, CoreSequence, IO; CoreSequenceImpl: CEDAR PROGRAM IMPORTS CoreClasses, CoreOps, CoreProperties, IO EXPORTS CoreSequence = BEGIN OPEN Core, CoreSequence; sequenceCellClass: PUBLIC CellClass _ NEW[CellClassRec _ [name: "Sequence", recast: Recast, properties: CoreProperties.Props[[CoreOps.printClassProcProp, NEW[CoreOps.PrintClassProc _ PropPrintClass]]]]]; Recast: RecastProc = { seqCell: SequenceCellType _ NARROW[me.data]; recCell: CoreClasses.RecordCellType _ NEW[CoreClasses.RecordCellTypeRec]; stitchesLength: NAT _ IF seqCell.stitches#NIL THEN seqCell.stitches.length ELSE 0; new _ CoreOps.CreateCellType[ class: CoreClasses.recordCellClass, public: CoreOps.CopyWireSequence[me.public], data: recCell, name: CoreOps.GetCellTypeName[me], props: CoreProperties.CopyProps[propList: me.properties]]; recCell.internal _ NEW [WireSequenceRec[new.public.size + stitchesLength]]; FOR w: NAT IN [0..new.public.size) DO recCell.internal[w] _ new.public[w]; ENDLOOP; FOR w: NAT IN [new.public.size .. recCell.internal.size) DO recCell.internal[w] _ NEW[WireRec]; CoreProperties.PutWireProp[recCell.internal[w], CoreOps.sequenceProp, CoreOps.sequenceProp]; recCell.internal[w].elements _ NEW[WireSequenceRec[seqCell.count]]; ENDLOOP; FOR cell: NAT IN [0..seqCell.count) DO newWire: WireSequence _ NEW [WireSequenceRec[new.public.size] _ new.public^]; FOR seqWire: NAT IN [0..seqCell.length) DO seqElement: NAT _ seqCell.sequence[seqWire]; IF CoreProperties.GetWireProp[seqCell.base.public[seqElement], CoreOps.sequenceProp]#NIL THEN { size: NAT _ seqCell.base.public[seqElement].elements.size; actWire: Wire _ NEW [WireRec _ [ elements: NEW [WireSequenceRec[size]]]]; CoreProperties.PutWireProp[actWire, CoreOps.sequenceProp, CoreOps.sequenceProp]; FOR i: NAT IN [0..size) DO actWire.elements[i] _ newWire[seqElement].elements[(size*cell)+i]; ENDLOOP; newWire[seqElement] _ actWire; } ELSE newWire[seqElement] _ newWire[seqElement].elements[cell]; ENDLOOP; IF stitchesLength>0 THEN ERROR; -- not yet implemented FOR stitchWire: NAT IN [0..stitchesLength) DO internal: Wire; IF cell < seqCell.count -1 THEN { internal _ CoreOps.CopyWire[wire: seqCell.base.public[seqCell.stitches[stitchWire].source]]; recCell.internal[stitchWire + new.public.size].elements[cell] _ internal; newWire[seqCell.stitches[stitchWire].source] _ internal; }; IF cell > 0 THEN newWire[seqCell.stitches[stitchWire].sink] _ recCell.internal[stitchWire + new.public.size].elements[cell-1]; ENDLOOP; recCell.instances _ CONS [ NEW [CoreClasses.CellInstanceRec _ [ actual: newWire, type: seqCell.base, properties: CoreProperties.Props[[CoreClasses.instanceNameProp, IF CoreOps.GetCellTypeName[seqCell.base]=NIL THEN NIL ELSE IO.PutFR["%g%g", IO.rope[CoreOps.GetCellTypeName[seqCell.base]], IO.int[cell]]]] ]], recCell.instances]; ENDLOOP; }; Create: PUBLIC PROC [args: SequenceCellType, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [cellType: CellType] = { cellType _ CoreOps.CreateCellType[ class: sequenceCellClass, public: CoreOps.CopyWireSequence[args.base.public], data: args, name: name, props: props]; FOR i: NAT IN [0..args.length) DO wire: Wire _ cellType.public[args.sequence[i]]; IF CoreProperties.GetWireProp[wire, CoreOps.sequenceProp]#NIL THEN { newSeqLength: NAT _ args.count * wire.elements.size; newSeq: WireSequence _ NEW[WireSequenceRec[newSeqLength]]; base: Wire _ wire.elements[0]; FOR i: NAT IN [0..newSeqLength) DO newSeq[i] _ CoreOps.CopyWire[wire: base]; ENDLOOP; cellType.public[args.sequence[i]].elements _ newSeq; } ELSE { newWire: Wire _ CoreOps.CreateBasicSequenceWire[args.count, CoreOps.GetWireName[wire]]; FOR i: NAT IN [0..args.count) DO newWire.elements[i] _ CoreOps.CopyWire[wire: wire]; ENDLOOP; cellType.public[args.sequence[i]] _ newWire; }; ENDLOOP; }; PropPrintClass: CoreOps.PrintClassProc = {Print[NARROW[data], out]}; Print: PUBLIC PROC [cell: SequenceCellType, out: IO.STREAM] = { IO.PutF[out, "\n\nBase cell type: %g", IO.rope[CoreOps.GetCellTypeName[cell.base]]]; IO.PutF[out, ", count: %g", IO.int[cell.count]]; IO.PutRope[out, "\nstitch wires:"]; IF cell.stitches#NIL THEN FOR stitch: NAT IN [0 .. cell.stitches.length) DO IO.PutF[out, " (%g, %g)", IO.rope[CoreOps.GetWireName[cell.base.public[cell.stitches[stitch].source]]], IO.rope[CoreOps.GetWireName[cell.base.public[cell.stitches[stitch].sink]]]]; ENDLOOP; IO.PutRope[out, "\nsequence wires:"]; FOR seq: NAT IN [0 .. cell.length) DO IO.PutF[out, " %g", IO.rope[CoreOps.GetWireName[cell.base.public[cell[seq]]]]]; ENDLOOP; }; END.