<> <> <> DIRECTORY Core; CoreClasses: CEDAR DEFINITIONS = BEGIN OPEN Core; <> <> <> <> <> <<1) For each instance the actual field must conform to the public field of the cell type which is pointed to by the instance.>> <> <> <> <> <> <<>> <<2) The wires of each actual field must point to wires that are reachable from the internal of the RecordCell.>> <<3) The public of the CellType must point to wires that are reachable from the internal of the RecordCell.>> recordCellClass: CellClass; RecordCellType: TYPE = REF RecordCellTypeRec; RecordCellTypeRec: TYPE = RECORD [ internal: WireSequence, instances: CellInstanceList _ NIL]; CellInstance: TYPE = REF CellInstanceRec; CellInstanceList: TYPE = LIST OF CellInstance; CellInstanceRec: TYPE = RECORD [ actual: WireSequence, type: CellType, properties: Properties _ NIL]; instanceNameProp: ATOM; -- for naming the instance RecordPrint: PROC [recordCellType: RecordCellType, out: STREAM]; CorrespondingActual: PROC [instance: CellInstance, public: Wire] RETURNS [actual: Wire _ NIL]; <> Bound: PROC [instance1, instance2: CellInstance, public1, public2: Wire] RETURNS [b: BOOL]; <> internalFullName: ATOM; <> <> <> <<>> transistorCellClass: CellClass; Transistor: TYPE = REF TransistorRec; TransistorRec: TYPE = RECORD [ type: TransistorType _ nE, length: NAT _ 2, width: NAT _ 4]; TransistorType: TYPE = {nE, pE, nD}; <> TransistorCreate: PROC [args: TransistorRec] RETURNS [cellType: CellType]; <> identityCellClass: CellClass; Identity: PROC [cellType: CellType, name: ROPE, props: Properties _ NIL] RETURNS [identity: CellType]; <> <> <> unspecifiedCellClass: CellClass; <<>> END.