<> <> <> <> <<>> <> <<>> DIRECTORY Core USING [CellType, ROPE, Wire, WireSequence], CoreClasses USING [CellInstance, TransistorType]; CoreBeau: CEDAR DEFINITIONS = BEGIN <> CellType: TYPE = Core.CellType; ROPE: TYPE = Core.ROPE; Wire: TYPE = Core.Wire; WireSequence: TYPE = Core.WireSequence; CellInstance: TYPE = CoreClasses.CellInstance; TransistorType: TYPE = CoreClasses.TransistorType; <> WR: TYPE = REF; <> <<>> Wires: PROC [wr1, wr2, wr3, wr4, wr5, wr6, wr7: WR _ NIL] RETURNS [WireSequence]; <> <<>> Seq: PROC [wr: WR, length: NAT] RETURNS [WireSequence]; <> <<>> Index: PROC [wr: WR, index: NAT] RETURNS [WR]; <> <<>> Indexes: PROC [wr: WR, start: NAT _ 0, length: NAT] RETURNS [WireSequence]; <> <<>> <> PA: TYPE = RECORD [public, actual: WR]; <> <<>> Instance: PROC [type: CellType, pa1, pa2, pa3, pa4, pa5, pa6: PA _ []] RETURNS [CellInstance]; <> <<>> Cell: PROC [name: ROPE _ NIL, public, onlyInternal: WireSequence _ NIL, instances: LIST OF CellInstance] RETURNS [CellType]; <> <> Transistor: PROC [name: ROPE _ NIL, type: TransistorType _ nE, length: NAT _ 2, width: NAT _ 4] RETURNS [CellType]; <> <<>> SequenceCell: PROC [name: ROPE _ NIL, baseCell: CellType, count: NAT, sequencePorts: WireSequence _ NIL] RETURNS [CellType]; <> <> FindWire: PROC [cell: CellType, wr: WR] RETURNS [Wire]; <> END.