CoreArrayImpl.mesa
Copyright © 1985 by Xerox Corporation. All rights reserved.
Barth, August 16, 1985 6:00:10 pm PDT
DIRECTORY Core, CoreArray, CoreOps, CoreProperties;
CoreArrayImpl:
CEDAR
PROGRAM
IMPORTS CoreOps, CoreProperties
EXPORTS CoreArray =
BEGIN OPEN Core, CoreArray;
arrayCellClass: PUBLIC CellClass ← NEW[CellClassRec ← [name: "Array", recast: RecastArray, write: WriteArray, read: ReadArray]];
Start:
PROC = {
CoreOps.RegisterCellClass[arrayCellClass];
arrayCellClass.properties ← CoreProperties.PutProp[on: arrayCellClass.properties, prop: CoreOps.printClassProcProp, value: NEW[CoreOps.PrintClassProc ← PropPrint]];
};
WriteArray: WriteProc = {
};
ReadArray: ReadProc = {
};
RecastArray: RecastProc = {
seqCell: SequenceCell ← NARROW[me.data];
recCell: CoreRecordCells.RecordCell ← NEW[CoreRecordCells.RecordCellRec];
new ← NEW[CellTypeRec ← [
name: me.name,
class: CoreRecordCells.recordCellClass,
publicWire: CoreOps.CopyWire[wire: me.publicWire],
data: recCell,
properties: CoreProperties.CopyProps[propList: me.properties]]];
recCell.internalWire ← NEW[WireRec ← [
structure: sequence]];
recCell.internalWire.elements ← NEW[WireSequenceRec[new.publicWire.elements.size + seqCell.stitches.length]];
FOR w: NAT IN [0..new.publicWire.elements.size) DO
recCell.internalWire.elements[w] ← new.publicWire.elements[w];
ENDLOOP;
FOR w: NAT IN [new.publicWire.elements.size..recCell.internalWire.elements.size) DO
recCell.internalWire.elements[w] ← NEW[WireRec ← [structure: sequence]];
recCell.internalWire.elements[w].elements ← NEW[WireSequenceRec[ seqCell.count]];
ENDLOOP;
FOR cell: NAT IN [0..seqCell.count) DO
newWire: Wire ← NEW[WireRec ← new.publicWire^];
newWire.elements ← NEW[WireSequenceRec[new.publicWire.elements.size] ← new.publicWire.elements^];
FOR seqWire:NAT IN [0..seqCell.length) DO
newWire.elements[seqCell.sequence[seqWire]] ← newWire.elements[seqCell.sequence[seqWire]].elements[cell];
ENDLOOP;
FOR stitchWire: NAT IN [0..seqCell.stitches.length) DO
internal: Wire;
IF cell < seqCell.count -1 THEN {
internal ← CoreOps.CopyWire[wire: seqCell.base.publicWire.elements[seqCell.stitches[stitchWire].source]];
recCell.internalWire.elements[stitchWire + new.publicWire.elements.size].elements[cell] ← internal;
newWire.elements[seqCell.stitches[stitchWire].source] ← internal;
};
IF cell > 0 THEN newWire.elements[seqCell.stitches[stitchWire].sink] ← recCell.internalWire.elements[stitchWire + new.publicWire.elements.size].elements[cell-1];
ENDLOOP;
recCell.instances ← CONS[NEW[CoreRecordCells.InstanceRec ← [
name: IF seqCell.base.name=NIL THEN NIL ELSE IO.PutFR["%g%g", IO.rope[seqCell.base.name], IO.int[cell]],
actualWire: newWire,
type: seqCell.base]],
recCell.instances];
ENDLOOP;
};
Create:
PUBLIC
PROC [arrayCellType: ArrayCellType, name:
ROPE ←
NIL]
RETURNS [cellType: CellType] = {
ArrayWire: PROC [sequence: Ports, parent: Wire, count: NAT] = {
FOR i:NAT IN [0..sequence.length) DO
wire: Wire ← parent.elements[sequence[i]];
newWire: Wire ← CoreOps.CreateSequenceWire[name: wire.name, base: wire, count: count];
parent.elements[sequence[i]] ← newWire;
ENDLOOP;
};
cellType ← NEW[CellTypeRec ← [
name: name,
class: arrayCellClass,
publicWire: CoreOps.CopyWire[wire: arrayCellType.cellTypes[0].publicWire],
data: arrayCellType]];
ArrayWire[sequence: arrayCellType.xparams.sequence, parent: cellType.publicWire, count: arrayCellType.xparams.count];
ArrayWire[sequence: arrayCellType.yparams.sequence, parent: cellType.publicWire, count: arrayCellType.yparams.count];
};
PropPrint: CoreOps.PrintClassProc = {
Print[NARROW[data], out];
};
Print:
PUBLIC
PROC [arrayCellType: ArrayCellType, out:
STREAM] = {
PrintParams: PROC [params: ArrayParams] = {
IO.PutF[out, "\n count: %g", IO.int[params.count]];
IO.PutRope[out, "\n sequence ports:"];
FOR seq: NAT IN [0..params.sequence.length) DO
IO.PutF[out, " %g", IO.rope[arrayCellType.cellTypes[0].publicWire.elements[ params.sequence[seq]].name]];
ENDLOOP;
IO.PutRope[out, "\n stitch ports:"];
FOR stitch: NAT IN [0..params.stitch.length) DO
IO.PutF[out, " (%g, %g)", IO.rope[arrayCellType.cellTypes[0].publicWire.elements[ params.stitch[stitch].a].name], IO.rope[arrayCellType.cellTypes[0].publicWire.elements[ params.stitch[stitch].b].name]];
ENDLOOP;
IO.PutRope[out, "\n bind ports:"];
FOR stitch: NAT IN [0..params.stitch.length) DO
IO.PutF[out, " (%g, %g)", IO.rope[arrayCellType.cellTypes[0].publicWire.elements[ params.stitch[stitch].a].name], IO.rope[arrayCellType.cellTypes[0].publicWire.elements[ params.stitch[stitch].b].name]];
ENDLOOP;
};
IO.PutRope[out, "\nX parameters"];
PrintParams[params: arrayCellType.xparams];
IO.PutRope[out, "\nY parameters"];
PrintParams[params: arrayCellType.yparams];
IF arrayCellType.select#NIL THEN IO.PutRope[out, "\nSelect procedure present"];
IO.PutRope[out, "\nBase cell types: "];
FOR cellType: NAT IN [0..arrayCellType.length) DO
IO.PutF[out, " %g", IO.rope[arrayCellType.cellTypes[cellType].name]];
ENDLOOP;
};
Start[];
END.