DIRECTORY Core, CoreClasses;CoreCreate: CEDAR DEFINITIONS = BEGINCellType: TYPE = Core.CellType;Properties: TYPE = Core.Properties;ROPE: TYPE = Core.ROPE;Wire: TYPE = Core.Wire;CellInstances: TYPE = CoreClasses.CellInstances;CellInstance: TYPE = CoreClasses.CellInstance;TransistorType: TYPE = CoreClasses.TransistorType;WR: TYPE = REF _ NIL;WireList: PROC [wrs: LIST OF WR _ NIL, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [Wire];Wires: PROC [wr1, wr2, wr3, wr4, wr5, wr6, wr7, wr8, wr9, wr10, wr11, wr12, wr13: WR _ NIL, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [Wire];Seq: PROC [name: ROPE _ NIL, size: NAT, protoChild: Wire _ NIL] RETURNS [Wire];Index: PROC [wr: WR, index: NAT] RETURNS [WR];Range: PROC [wire: Wire, start, size: NAT, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [Wire];Union: PROC [wr1, wr2, wr3, wr4, wr5, wr6, wr7, wr8, wr9, wr10, wr11, wr12, wr13: Wire _ NIL, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [Wire];PA: TYPE = RECORD [public, actual: WR];Instance: PROC [type: CellType, pa1, pa2, pa3, pa4, pa5, pa6, pa7, pa8, pa9, pa10, pa11, pa12, pa13: PA _ [], name: ROPE _ NIL, props: Properties _ NIL] RETURNS [CellInstance];InstanceList: PROC [type: CellType, pas: LIST OF PA _ NIL, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [CellInstance];Cell: PROC [public: Wire, onlyInternal, internal: Wire _ NIL, instances: CellInstances, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [CellType];Transistor: PROC [type: TransistorType _ nE, length: NAT _ 2, width: NAT _ 4, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [CellType];SequenceCell: PROC [baseCell: CellType, count: NAT, sequencePorts: Wire _ NIL, flatSequencePorts: Wire _ NIL, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [CellType];FindWire: PROC [root: Wire, wr: WR] RETURNS [Wire];END.   ║  CoreCreate.mesaCopyright c 1985 by Xerox Corporation.  All rights reserved.Bertrand Serlet, March 20, 1986 0:22:06 am PSTBarth, May 7, 1986 10:17:04 am PDTLouis Monier March 12, 1986 9:59:34 am PSTTheoryThis interface provides syntactic sugar to help create Core data structures while retaining the ability to have handles on the real Core objects.TypesWiresWR is the union of the types Wire and ROPE, for user convenience.  Basic constructor for creating a structured wire.  Each element of wrs must be of type Wire or ROPE.Same as WireList but with more sugar.  Each wr must be of type Wire or ROPE.Creates a wire with size children.  protoChild#NIL => CoreOps.CopyWire is used to make children. Extractor for extracting a wire from a sequence.  If the argument is a Wire then the element is extracted.  If the argument is a ROPE, the suffix "[index]" is added to it.  wr must be of type Wire or ROPE.Extractor for extracting a group of wires from a sequence.  Elements are extracted and grouped together.  The argument must be of type Wire only.Creates flat union of arguments.CellsRecords a binding.Creates a CoreClasses.RecordCell. If internal=NIL then internal _ Union[public, onlyInternal].If internal#NIL then onlyInternal is discarded.Creates a CoreClasses.Transistor.Creates a CoreSequence.SequenceCellType.Getting handles on real wiresLooks into root to find wr.  Root should usually be a public or an internal.Э╩f  Ш codeЪЬЩKЪЬ
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