DIRECTORY Core, CoreClasses, CoreContext, SymTab; CoreCompose: CEDAR DEFINITIONS = BEGIN ROPE: TYPE = Core.ROPE; Wire: TYPE = Core.Wire; CellType: TYPE = Core.CellType; TransistorType: TYPE = CoreClasses.TransistorType; InstanceList: TYPE = LIST OF InstanceRec; InstanceRec: TYPE = RECORD[ actual: ROPE, -- need a parser to turn it into actual wires type: CellType]; Context: TYPE = CoreContext.Context; -- SymTab of [rope, tv] PropertyLiteral: TYPE = RECORD[key: ATOM, val: REF]; PropertyLiterals: TYPE = LIST OF PropertyLiteral; GetRef: PROC [context: Context, name: ROPE] RETURNS [REF]; GetAtom: PROC [context: Context, name: ROPE] RETURNS [ATOM]; GetRope: PROC [context: Context, name: ROPE] RETURNS [ROPE]; GetInt: PROC [context: Context, name: ROPE] RETURNS [INT]; GetReal: PROC [context: Context, name: ROPE] RETURNS [REAL]; GetBool: PROC [context: Context, name: ROPE] RETURNS [BOOL]; PushRef: PROC [context: Context, name: ROPE, val: REF]; PushAtom: PROC [context: Context, name: ROPE, val: ATOM]; PushRope: PROC [context: Context, name: ROPE, val: ROPE]; PushInt: PROC [context: Context, name: ROPE, val: INT]; PushReal: PROC [context: Context, name: ROPE, val: REAL]; PushBool: PROC [context: Context, name: ROPE, val: BOOL]; CreateTransistor: PROC [name: ROPE _ NIL, type: TransistorType _ nE, length: NAT _ 2, width: NAT _ 4] RETURNS [cellType: CellType]; CreateRecordCell: PROC [name: ROPE, public: Wire, onlyInternal: Wire _ NIL, instances: InstanceList _ NIL, context: Context _ NIL] RETURNS [cellType: CellType]; CreateSequenceCell: PROC [name: ROPE, baseCell: CellType, count: NAT, sequencePorts: ROPE _ NIL] RETURNS [cellType: CellType]; CreateWires: PROC [rope: ROPE, context: Context _ NIL] RETURNS [wire: Wire]; END. Example: ct _ MakeEU[context, 3, 5]; ct _ Sisyph.Extract[context, name]; \CoreCompose.mesa Copyright c 1985 by Xerox Corporation. All rights reserved. Barth, October 15, 1985 3:40:50 pm PDT Bertrand Serlet November 26, 1985 11:48:56 am PST Louis Monier December 17, 1985 2:10:54 pm PST Common Types and Errors -- A Context is a stack of properties Context Cells Wires -- Uses the parser Theory This interface provides some procedures useful for assembling elementary Core object into more complex ones. It also provides for user comfort a number of short cuts which increase the readability of Core-producing code. What follows is the grammar of the language used inside ropes that define wire (public or internal) and actual (binding). publicOrInternal_" M[ Data[seq:32][a, b[seq:2]], -- seq of record Other[seq:32], -- seq of unnamed atomic Cmd[enum:Dragon.MBusCommands], -- enumerated type Hold], -- atomic Vdd, -- atomic Input[x, y]" -- record of two atomic actual _ " a:M.Data[3].b[0], -- bunch of subfield and subrange chasing b:M.Data[start:1, len:7], -- subrange c:[M.Hold, M.Cmd]" -- composed wire (not implemented yet) publicOrInternal ::= composition ,.. composition ::= name ( [ sequence ] )* ?( [ publicOrInternal ] ) | name [ enumType ] sequence ::= seq: exp enumType ::= enum: enumeratedTypeName -- whatever the interpreter will buy binding ::= name : actual ,.. actual ::= name ( selector )* ?( [ start: exp, len: exp ] ) | [ actual ,.. ] selector ::= .name | [ exp ] name ::= a valid Cedar identifier exp ::= a valid expression evaluating to an integer Notes: Semantic of ENUM? Do we want to sequence an enumerated type? Κ2˜– "Cedar" stylešœ™Icode– "Cedar" stylešœ Οmœ1™Kš œžœžœžœžœ˜4Kšœžœžœžœ˜1—™Kš Οnœžœžœžœžœ˜:Kš ‘œžœžœžœžœ˜