DIRECTORY Core, CoreArray, CoreOps, CoreProperties; CoreArrayImpl: CEDAR PROGRAM IMPORTS CoreOps, CoreProperties EXPORTS CoreArray = BEGIN OPEN Core, CoreArray; arrayCellClass: PUBLIC CellClass _ NEW[CellClassRec _ [name: "Array", recast: RecastArray, write: WriteArray, read: ReadArray]]; Start: PROC = { CoreOps.RegisterCellClass[arrayCellClass]; arrayCellClass.properties _ CoreProperties.PutProp[on: arrayCellClass.properties, prop: CoreOps.printClassProcProp, value: NEW[CoreOps.PrintClassProc _ PropPrint]]; }; WriteArray: WriteProc = { }; ReadArray: ReadProc = { }; RecastArray: RecastProc = { }; Create: PUBLIC PROC [arrayCellType: ArrayCellType, name: ROPE _ NIL] RETURNS [cellType: CellType] = { }; PropPrint: CoreOps.PrintClassProc = { Print[NARROW[data], out]; }; Print: PUBLIC PROC [arrayCellType: ArrayCellType, out: STREAM] = { }; Start[]; END. CoreArrayImpl.mesa Copyright c 1985 by Xerox Corporation. All rights reserved. Barth, August 16, 1985 6:00:10 pm PDT seqCell: SequenceCell _ NARROW[me.data]; recCell: CoreRecordCells.RecordCell _ NEW[CoreRecordCells.RecordCellRec]; new _ NEW[CellTypeRec _ [ name: me.name, class: CoreRecordCells.recordCellClass, publicWire: CoreOps.CopyWire[wire: me.publicWire], data: recCell, properties: CoreProperties.CopyProps[propList: me.properties]]]; recCell.internalWire _ NEW[WireRec _ [ structure: sequence]]; recCell.internalWire.elements _ NEW[WireSequenceRec[new.publicWire.elements.size + seqCell.stitches.length]]; FOR w: NAT IN [0..new.publicWire.elements.size) DO recCell.internalWire.elements[w] _ new.publicWire.elements[w]; ENDLOOP; FOR w: NAT IN [new.publicWire.elements.size..recCell.internalWire.elements.size) DO recCell.internalWire.elements[w] _ NEW[WireRec _ [structure: sequence]]; recCell.internalWire.elements[w].elements _ NEW[WireSequenceRec[ seqCell.count]]; ENDLOOP; FOR cell: NAT IN [0..seqCell.count) DO newWire: Wire _ NEW[WireRec _ new.publicWire^]; newWire.elements _ NEW[WireSequenceRec[new.publicWire.elements.size] _ new.publicWire.elements^]; FOR seqWire:NAT IN [0..seqCell.length) DO newWire.elements[seqCell.sequence[seqWire]] _ newWire.elements[seqCell.sequence[seqWire]].elements[cell]; ENDLOOP; FOR stitchWire: NAT IN [0..seqCell.stitches.length) DO internal: Wire; IF cell < seqCell.count -1 THEN { internal _ CoreOps.CopyWire[wire: seqCell.base.publicWire.elements[seqCell.stitches[stitchWire].source]]; recCell.internalWire.elements[stitchWire + new.publicWire.elements.size].elements[cell] _ internal; newWire.elements[seqCell.stitches[stitchWire].source] _ internal; }; IF cell > 0 THEN newWire.elements[seqCell.stitches[stitchWire].sink] _ recCell.internalWire.elements[stitchWire + new.publicWire.elements.size].elements[cell-1]; ENDLOOP; recCell.instances _ CONS[NEW[CoreRecordCells.InstanceRec _ [ name: IF seqCell.base.name=NIL THEN NIL ELSE IO.PutFR["%g%g", IO.rope[seqCell.base.name], IO.int[cell]], actualWire: newWire, type: seqCell.base]], recCell.instances]; ENDLOOP; ArrayWire: PROC [sequence: Ports, parent: Wire, count: NAT] = { FOR i:NAT IN [0..sequence.length) DO wire: Wire _ parent.elements[sequence[i]]; newWire: Wire _ CoreOps.CreateSequenceWire[name: wire.name, base: wire, count: count]; parent.elements[sequence[i]] _ newWire; ENDLOOP; }; cellType _ NEW[CellTypeRec _ [ name: name, class: arrayCellClass, publicWire: CoreOps.CopyWire[wire: arrayCellType.cellTypes[0].publicWire], data: arrayCellType]]; ArrayWire[sequence: arrayCellType.xparams.sequence, parent: cellType.publicWire, count: arrayCellType.xparams.count]; ArrayWire[sequence: arrayCellType.yparams.sequence, parent: cellType.publicWire, count: arrayCellType.yparams.count]; PrintParams: PROC [params: ArrayParams] = { IO.PutF[out, "\n count: %g", IO.int[params.count]]; IO.PutRope[out, "\n sequence ports:"]; FOR seq: NAT IN [0..params.sequence.length) DO IO.PutF[out, " %g", IO.rope[arrayCellType.cellTypes[0].publicWire.elements[ params.sequence[seq]].name]]; ENDLOOP; IO.PutRope[out, "\n stitch ports:"]; FOR stitch: NAT IN [0..params.stitch.length) DO IO.PutF[out, " (%g, %g)", IO.rope[arrayCellType.cellTypes[0].publicWire.elements[ params.stitch[stitch].a].name], IO.rope[arrayCellType.cellTypes[0].publicWire.elements[ params.stitch[stitch].b].name]]; ENDLOOP; IO.PutRope[out, "\n bind ports:"]; FOR stitch: NAT IN [0..params.stitch.length) DO IO.PutF[out, " (%g, %g)", IO.rope[arrayCellType.cellTypes[0].publicWire.elements[ params.stitch[stitch].a].name], IO.rope[arrayCellType.cellTypes[0].publicWire.elements[ params.stitch[stitch].b].name]]; ENDLOOP; }; IO.PutRope[out, "\nX parameters"]; PrintParams[params: arrayCellType.xparams]; IO.PutRope[out, "\nY parameters"]; PrintParams[params: arrayCellType.yparams]; IF arrayCellType.select#NIL THEN IO.PutRope[out, "\nSelect procedure present"]; IO.PutRope[out, "\nBase cell types: "]; FOR cellType: NAT IN [0..arrayCellType.length) DO IO.PutF[out, " %g", IO.rope[arrayCellType.cellTypes[cellType].name]]; ENDLOOP; Êè– "cedar" style˜codešœ™Kšœ Ïmœ1™™>Kšžœ™—šžœžœžœDž™SKšœ#žœ"™HKšœ,žœ"™QKšžœ™—šžœžœžœž™&Jšœžœ™/JšœžœK™ašžœ žœžœž™)Kšœi™iKšžœ™—šžœ žœžœž™6Kšœ™šžœžœ™!Kšœi™iKšœc™cKšœA™AK™—Kšžœ žœ‘™¡Kšžœ™—šœžœžœ ™