<> <> <> <> <> <> <> DIRECTORY Core; CoreOps: CEDAR DEFINITIONS = BEGIN OPEN Core; <> <> <> nameProp: ATOM; <> <> SetClassPrintProc: PROC [class: CellClass, proc: PrintClassProc] RETURNS [sameClass: CellClass]; PrintClassProc: TYPE = PROC [data: REF ANY, out: STREAM, indent: NAT _ 0, level: NAT _ 2]; <> CreateCellType: PROC [class: CellClass, public: Wire, data: REF ANY _ NIL, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [cellType: CellType]; SetCellTypeName: PROC [cellType: CellType, name: ROPE] RETURNS [sameCellType: CellType]; GetCellTypeName: PROC [cellType: CellType] RETURNS [name: ROPE]; Recast: RecastProc; <> ToBasic: PROC [cellType: Core.CellType] RETURNS [basic: Core.CellType]; <> PrintCellType: PROC [cellType: CellType, out: STREAM _ NIL, indent: NAT _ 0, level: NAT _ 2]; PrintIndent: PROC [indent: NAT, out: STREAM, cr: BOOL _ TRUE]; <> CreateWire: PROC [elements: Wires _ NIL, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [wire: Wire]; CreateWires: PROC [size: NAT, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [wire: Wire]; SubrangeWire: PROC [wire: Wire, start, size: NAT, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [sub: Wire]; CopyWire: PROC [wire: Wire] RETURNS [new: Wire]; <> UnionWire: PROC [wire1, wire2: Wire, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [union: Wire]; <> <> EachWireProc: TYPE = PROC [wire: Wire] RETURNS [subWires: BOOL _ TRUE, quit: BOOL _ FALSE]; EachWirePairProc: TYPE = PROC [actualWire, publicWire: Wire] RETURNS [subWires: BOOL _ TRUE, quit: BOOL _ FALSE]; VisitWire: PROC [wire: Wire, eachWire: EachWireProc] RETURNS [quit: BOOL]; <> <> VisitAtomicWires: PROC [wire: Wire, eachWire: PROC [Wire]]; <> <> VisitBinding: PROC [actual, public: Wire, eachWirePair: EachWirePairProc] RETURNS [quit: BOOL]; <> Conform: PROC [actual, public: Wire] RETURNS [BOOL]; <> <<>> WireBits: PROC [wire: Wire] RETURNS [bits: NAT]; <> <> <> <<>> SetShortWireName: PROC [wire: Wire, name: ROPE] RETURNS [sameWire: Wire]; GetShortWireName: PROC [wire: Wire] RETURNS [name: ROPE]; GetWireIndex: PROC [wire: Wire, name: ROPE] RETURNS [n: INT _ -1]; <> GetFullWireNames: PROC [root, wire: Wire] RETURNS [names: LIST OF ROPE]; <> GetFullWireName: PROC [root, wire: Wire] RETURNS [name: ROPE]; <> <> <> IsFullWireName: PROC [root, wire: Wire, name: ROPE] RETURNS [BOOL]; FindWire: PROC [root: Wire, name: ROPE] RETURNS [wire: Wire _ NIL]; <> ParseWireName: PROC [name: ROPE] RETURNS [base: ROPE, components: LIST OF ROPE _ NIL]; <> PrintWire: PROC [wire: Wire, out: STREAM _ NIL, indent: NAT _ 0, level: NAT _ 2]; FlushNameCaches: PROC [root: Wire]; <> <> Reverse: PROC [wires: Wires] RETURNS [revWires: Wires _ NIL]; Delete: PROC [wires: Wires, wire: Wire] RETURNS [newWires: Wires _ NIL]; Member: PROC [wires: Wires, wire: Wire] RETURNS [BOOL]; <> <<>> RecursiveMember: PROC [wire, candidate: Wire] RETURNS [BOOL]; <> <> FixStupidRef: PROC [ref: REF ANY] RETURNS [rope: ROPE]; <> <<>> Print: PROC [ref: REF, out: STREAM _ NIL, indent: NAT _ 0, level: NAT _ 2]; <> END.