CoreOps.mesa
Copyright © 1985 by Xerox Corporation. All rights reserved.
Barth, January 28, 1986 3:33:03 pm PST
Bertrand Serlet May 29, 1986 7:31:55 pm PDT
Spreitzer, April 8, 1986 4:29:54 pm PST
Louis Monier May 1, 1986 4:43:54 pm PDT
Pradeep Sindhu February 7, 1986 3:20:36 pm PST
Cell Classes
SetClassPrintProc:
PROC [class: CellClass, proc: PrintClassProc]
RETURNS [sameClass: CellClass];
PrintClassProc: TYPE = PROC [data: REF ANY, out: STREAM, indent: NAT ← 0, level: NAT ← 2];
Cell Types
CreateCellType:
PROC [class: CellClass, public: Wire, data:
REF
ANY ←
NIL, name:
ROPE ←
NIL, props: Properties ←
NIL]
RETURNS [cellType: CellType];
SetCellTypeName:
PROC [cellType: CellType, name:
ROPE]
RETURNS [sameCellType: CellType];
GetCellTypeName:
PROC [cellType: CellType]
RETURNS [name:
ROPE];
Recast: RecastProc;
Always returns the same pointer, given same cell type.
ToBasic:
PROC [cellType: Core.CellType]
RETURNS [basic: Core.CellType];
Recasts as much as possible.
PrintCellType:
PROC [cellType: CellType, out:
STREAM ←
NIL, indent:
NAT ← 0, level:
NAT ← 2];
PrintIndent: PROC [indent: NAT, out: STREAM, cr: BOOL ← TRUE];
Wire Creation
CreateWire:
PROC [elements: Wires ←
NIL, name:
ROPE ←
NIL, props: Properties ←
NIL]
RETURNS [wire: Wire];
CreateWires:
PROC [size:
NAT, name:
ROPE ←
NIL, props: Properties ←
NIL]
RETURNS [wire: Wire];
SubrangeWire:
PROC [wire: Wire, start, size:
NAT, name:
ROPE ←
NIL, props: Properties ←
NIL]
RETURNS [sub: Wire];
CopyWire:
PROC [wire: Wire]
RETURNS [new: Wire];
Properties are copied using CoreProperties.CopyProps
UnionWire:
PROC [wire1, wire2: Wire, name:
ROPE ←
NIL, props: Properties ←
NIL]
RETURNS [union: Wire];
Creates a new structured wire of size wire1.size+wire2.size, with corresponding name and properties
Wire Enumeration
EachWireProc:
TYPE =
PROC [wire: Wire]
RETURNS [subWires:
BOOL ←
TRUE, quit:
BOOL ←
FALSE];
EachWirePairProc:
TYPE =
PROC [actualWire, publicWire: Wire]
RETURNS [subWires:
BOOL ←
TRUE, quit:
BOOL ←
FALSE];
VisitWire:
PROC [wire: Wire, eachWire: EachWireProc]
RETURNS [quit:
BOOL];
Returns quit iff eachWire did.
Visits the wire as a tree: each subwire reachable n ways is reached each of those n ways.
VisitAtomicWires:
PROC [wire: Wire, eachWire:
PROC [Wire]];
Short for previous function, when only atomic wires should be enumerated, and when the quit argument is not needed.
Visits the wire as a tree: each subwire reachable n ways is reached each of those n ways.
VisitBinding:
PROC [actual, public: Wire, eachWirePair: EachWirePairProc]
RETURNS [quit:
BOOL];
Visits two wires as trees in parallel. Aborts visit and returns quit=TRUE iff eachWirePair returns quit=TRUE or differing structure (viewed as trees) found.
Conform:
PROC [actual, public: Wire]
RETURNS [
BOOL];
Works only for trees, not DAGs; checks that they have the same structure.
WireBits:
PROC [wire: Wire]
RETURNS [bits:
NAT];
Computes the number of atomic wires reachable from wire.
Wire Naming
Wires have attached 2 kinds of names: short names (at most one per wire) and full names, which are relative to a root wire (such as public or internal), and which are a list of ROPE since we have DAGs.
SetShortWireName:
PROC [wire: Wire, name:
ROPE]
RETURNS [sameWire: Wire];
GetShortWireName:
PROC [wire: Wire]
RETURNS [name:
ROPE];
GetWireIndex:
PROC [wire: Wire, name:
ROPE]
RETURNS [n:
INT ← -1];
If wire is not atomic, and wire[i] has short name "name" , then returns "i"; -1 if not found.
GetFullWireNames:
PROC [root, wire: Wire]
RETURNS [names:
LIST
OF
ROPE];
Appends .name if a short name is on the wire otherwise appends [index]. Should only be called with root DAGs, e.g. a public wire. Full path names relative to the root DAG are cached (property on the root).
GetFullWireName:
PROC [root, wire: Wire]
RETURNS [name:
ROPE];
Short for the previous one, when it is known that there is only and exactly one full name.
Will provoke an error when called with a wire that has 0 or more than one full name.
Should only be called with root DAGs, e.g. a public wire.
IsFullWireName:
PROC [root, wire: Wire, name:
ROPE]
RETURNS [
BOOL];
FindWire:
PROC [root: Wire, name:
ROPE]
RETURNS [wire: Wire ←
NIL];
Fetches a wire part of root with full name name. NIL is returned if no wire or more than one is found.
ParseWireName:
PROC [name:
ROPE]
RETURNS [base:
ROPE, components:
LIST
OF
ROPE ←
NIL];
Breaks apart a wire name into its components. Eg., given the name "foo.mumble[3].bar", base is "foo", and components is LIST["mumble", "3", "bar"].
PrintWire:
PROC [wire: Wire, out:
STREAM ←
NIL, indent:
NAT ← 0, level:
NAT ← 2];
FlushNameCaches:
PROC [root: Wire];
Various caches are stored on roots, and this function may get rid of them.
Wire List Operations
Reverse:
PROC [wires: Wires]
RETURNS [revWires: Wires ←
NIL];
Delete:
PROC [wires: Wires, wire: Wire]
RETURNS [newWires: Wires ←
NIL];
Member:
PROC [wires: Wires, wire: Wire]
RETURNS [
BOOL];
Searches for wire in the list wires.
RecursiveMember:
PROC [wire, candidate: Wire]
RETURNS [
BOOL];
Searches for candidate in the structured wire treeWire.