<> <> <> <> <> DIRECTORY Core, CoreClasses, CoreContext, SymTab; CoreCompose: CEDAR DEFINITIONS = BEGIN <> ROPE: TYPE = Core.ROPE; Wire: TYPE = Core.Wire; CellType: TYPE = Core.CellType; TransistorType: TYPE = CoreClasses.TransistorType; InstanceList: TYPE = LIST OF InstanceRec; InstanceRec: TYPE = RECORD[ actual: ROPE, -- need a parser to turn it into actual wires type: CellType]; <<-- A Context is a stack of properties>> Context: TYPE = CoreContext.Context; -- SymTab of [rope, tv] PropertyLiteral: TYPE = RECORD[key: ATOM, val: REF]; PropertyLiterals: TYPE = LIST OF PropertyLiteral; <> GetRef: PROC [context: Context, name: ROPE] RETURNS [REF]; GetAtom: PROC [context: Context, name: ROPE] RETURNS [ATOM]; GetRope: PROC [context: Context, name: ROPE] RETURNS [ROPE]; GetInt: PROC [context: Context, name: ROPE] RETURNS [INT]; GetReal: PROC [context: Context, name: ROPE] RETURNS [REAL]; GetBool: PROC [context: Context, name: ROPE] RETURNS [BOOL]; PushRef: PROC [context: Context, name: ROPE, val: REF]; PushAtom: PROC [context: Context, name: ROPE, val: ATOM]; PushRope: PROC [context: Context, name: ROPE, val: ROPE]; PushInt: PROC [context: Context, name: ROPE, val: INT]; PushReal: PROC [context: Context, name: ROPE, val: REAL]; PushBool: PROC [context: Context, name: ROPE, val: BOOL]; <> CreateTransistor: PROC [name: ROPE _ NIL, type: TransistorType _ nE, length: NAT _ 2, width: NAT _ 4] RETURNS [cellType: CellType]; CreateRecordCell: PROC [name: ROPE, public: Wire, onlyInternal: Wire _ NIL, instances: InstanceList _ NIL, context: Context _ NIL] RETURNS [cellType: CellType]; CreateSequenceCell: PROC [name: ROPE, baseCell: CellType, count: NAT, sequencePorts: ROPE _ NIL] RETURNS [cellType: CellType]; <> <<-- Uses the parser>> CreateWires: PROC [rope: ROPE, context: Context _ NIL] RETURNS [wire: Wire]; END. <> <> <> <> <> <> <> <> <> <> <<>> <> <> <> <> <<>> <> <> <> <> << >> <> <> <> <<>> <> <> <> <> <> Example: ct _ MakeEU[context, 3, 5]; ct _ Sisyph.Extract[context, name];