<> <> <> <> <> <> DIRECTORY Core; CoreClasses: CEDAR DEFINITIONS = BEGIN OPEN Core; <> <> <> <> <> <<1) The actual wire of an instance must conform to the public wire of the cell type which is pointed to by the instance.>> <<2) The actual field of an instance must point directly to a wire that is not reachable from the internal of the record cell. This wire, as is true of all public wires, must not be atomic and all of its subwires must be reachable from the internal of the cell type.>> <<3) The public field of a cell type of record cell class must point to a wire that is not reachable from the internal of the record cell. This wire, as is true of all public wires, must not be atomic and all of its subwires must be reachable from the internal of the cell type.>> <<4) The first level of the internal wire hierarchy exists only to allow smooth recursion, and to give a handle on the whole internal. Consequently, internal.size=0 should be interpreted as an empty internal and not an atomic wire. CoreOps naming strategy requires that internal are immutable, once part of a recordCell.>> recordCellClass: CellClass; RecordCellType: TYPE = REF RecordCellTypeRec; RecordCellTypeRec: TYPE = RECORD [ internal: Wire, instances: SEQUENCE size: NAT OF CellInstance]; <> <> CellInstance: TYPE = REF CellInstanceRec; CellInstanceRec: TYPE = RECORD [ actual: Wire, type: CellType, properties: Properties _ NIL]; <> CellInstances: TYPE = LIST OF CellInstance; CreateRecordCell: PROC [public: Wire, internal: Wire, instances: LIST OF CellInstance, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [recordCell: CellType]; <> CreateInstance: PROC [actual: Wire, type: CellType, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [instance: CellInstance]; SetCellInstanceName: PROC [instance: CellInstance, name: ROPE] RETURNS [sameInstance: CellInstance]; GetCellInstanceName: PROC [instance: CellInstance] RETURNS [name: ROPE]; CorrespondingActual: PROC [instance: CellInstance, public: Wire] RETURNS [actual: Wire _ NIL]; <> ReverseCellInstances: PROC [instances: CellInstances] RETURNS [rev: CellInstances _ NIL]; <> <> transistorCellClass: CellClass; Transistor: TYPE = REF TransistorRec; TransistorRec: TYPE = RECORD [ type: TransistorType _ nE, length: NAT _ 2, width: NAT _ 4]; TransistorType: TYPE = {nE, pE, nD}; TransistorPort: TYPE = MACHINE DEPENDENT {gate(0), ch1(1), ch2(2)}; transistorTypeNames: ARRAY TransistorType OF ROPE; transistorPortNames: ARRAY TransistorPort OF ROPE; <> CreateTransistor: PROC [args: TransistorRec, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [transistor: CellType]; <> <> identityCellClass: CellClass; CreateIdentity: PROC [cellType: CellType, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [identity: CellType]; <> <> unspecifiedCellClass: CellClass; CreateUnspecified: PROC [public: Wire _ NIL, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [cellType: CellType]; END.