SchematicExtractorDoc.tioga
Copyright © 1985 by Xerox Corporation. All rights reserved.
by Christian Jacobi, August 15, 1985 5:54:27 pm PDT
Last Edited by Christian Jacobi, August 20, 1985 5:22:06 pm PDT
Design methodology
A cell in the real world has two representations in the ChipNSil design. A schematic cell, showing its internal structure and a small iconic cell, showing a nice picture.
The ChipNSil design plane is only a drawing board; all the real information is contained in cells, independently if they are placed down or not.
A schematic cell has wires (black ChipNSil layer), iconic subcells (other ChipNSil cells), names (ChipNSil Text) and pins. Text or signal names on Instances evaluates in node names, given to the closest wire. Iconic subcells mean instances of real world subcells of the same name. The name of the schematic cell is not relevant; The schematic cell implements some real world cell, but its name is reserved for the Iconic representation. The schematic cell has a property $Implements which tells what real world cell it implements. Pins of a schematic cell denote that a touching wire should be public.
A schematic cell may have an $ConnectByName property (value is a rope, a list of names separated by space). These nodes are assumed even if not drawn. Actually, I think this feature is not useful.
An iconic cell has any nice picture which is completely meningless, except pins. The pins denote conducting area (same rules as black stuff), their name is the name of the public wire of the real world cell represented by the iconic cell. Iconic cells are supposed to have an $Represents property. It's value is a rope
extract {name of ChipNSil cell implementing it}
an empty name means check all the $Implements properties of all schematic cells.
use (name of cell in real world Design)
interpret (stuff to be feed to the interpreter)
the following idntifiers are predeclared: $design, $coreDesign, $ob
An iconic cell may have an $ConnectByName property (value is a rope, a list of names separated by space). These nodes will be assumed in the core data structure for the iconic cell, but wires are not drawn. These nodes are assumed connected to nodes of the schematic cell (which using the iconic instance) with the same name.
Wires are considered connected if one end touches an other wire anywere. Crossing wires are not connected. Restriction: the program looks at the wire Object, not the region of black stuff on the screen.
The interactive program
Use the <Space-P> Program menu and select ChipNSil extraction. The selected cell is considered a real cell and extracted.
The interface
Extract: PROC [design: CD.Design, what: REF←NIL, into: Core.Design←NIL, mode: REF←NIL];
what: Instance or Object
mode: Just for me recompiling less while experimenting; NIL is good; $output creates output on Terminal
into: Core design, if NIL design will be created, if not, design is used to get real world representation of iconic cells.
Problems
Connectin schematic to core is still not good
should the iconic cell say who implements it or should the schematic cell say which icon it implements?
Transistors have 3 wires to connect, but
Core misses functionality like
Compatibility check of cellTypes
Propagate change
Remove cellTypes
Replace cellTypes
Copy cellTypes, maybe into an other design
Rational
Useful to get test data structures.
In future useful as Schematic extractor