[Cyan]<DATools6.0>Boole>BooleTest.mesa!25

BooleTest.mesa

Created by Bertrand Serlet July 31, 1985 3:03:17 pm PDT

Last edited by Bertrand Serlet June 8, 1986 5:21:11 pm PDT

Barth, June 13, 1986 3:37:52 pm PDT

Louis Monier April 8, 1986 11:56:33 am PST

DIRECTORY

Boole, BooleCore, BooleCoreImpl, CD, CDProperties, Core, CoreClasses, CoreCreate, CoreOps, CoreProperties, PW, PWCore, Rope, Rosemary, RosemaryUser, Ports, Sisyph;

BooleTest: CEDAR PROGRAM

IMPORTS Boole, BooleCore, CDProperties, CoreCreate, CoreOps, CoreProperties, PW, PWCore, Rosemary, RosemaryUser, Ports, Sisyph

SHARES BooleCoreImpl =

BEGIN OPEN Boole, BooleCore;

Basic Test

Decoder: PUBLIC PROC [] RETURNS [result: Expression] = {

pBar: Expression ← true;

gBar: Expression ← true;

a, b, c, d: Expression;

plus, or, and, xor: Expression;

a ← Var["a"]; b ← Var["b"]; c ← Var["c"]; d ← Var["d"];

plus ← And[c, d];

xor ← And[Not[c], d];

and ← And[c, Not[d]];

or ← And[Not[c], Not[d]];

pBar ← If[plus, Xor[a, Not[b]], pBar];

gBar ← If[plus, Or[Not[a], Not[b]], gBar];

pBar ← If[or, Nor[a, b], pBar];

pBar ← If[and, Not[And[a, b]], pBar];

pBar ← If[xor, Xor[a, Not[b]], pBar];

result ← And[gBar, pBar];

};

Test of BooleCore

design: CD.Design ← BooleCore.cellLibrary;

cx: Sisyph.Context ← BooleCore.cx;

AlpsExtract: PROC [name: ROPE] RETURNS [cellType: CellType] ~ {

cellType ← Sisyph.ExtractSchematicByName[name: name, cx: cx];

PWCore.SetGet[cellType, design];

};

DecoderCellType: PUBLIC PROC [] RETURNS [recordCell: CellType] = {

inputDriver: CellType ← AlpsExtract["InputDriver.sch"];

outputDriver: CellType ← AlpsExtract["ClockedOutputDriver.sch"];

recordCell ← AlpsCell[

public: CoreCreate.Wires["a", "b", "c", "d", "r", "ab", "Gnd", "Vdd", "phiA", "phiB", "VRef"],

inputs: LIST [["a", inputDriver], ["b", inputDriver], ["c", inputDriver], ["d", inputDriver]],

outputs: LIST [

["r", Decoder[], outputDriver, LIST [["Clock", "phiA"], ["VRef", "VRef"]]],

["ab", And[Var["a"], Var["b"]], outputDriver, LIST [["Clock", "phiB"], ["VRef", "VRef"]]]

props: CoreProperties.Props[[$ContactPolyMetal2, NEW [INT ← 3]]]

];

};

a, b, c, d, r, ab, Gnd, Vdd, phiA, phiB, VRef: NAT;

RopeLevel: TYPE = RECORD [rope: ROPE, level: Ports.Level];

Ev: PROC [expr: Expression, rls: LIST OF RopeLevel] RETURNS [Expression] = {

SELECT TRUE FROM

rls=NIL => RETURN [expr];

rls.first.level=X => RETURN [Ev[expr, rls.rest]];

rls.first.level=H => RETURN [Ev[Boole.Eval[rls.first.rope, expr].whenTrue, rls.rest]];

rls.first.level=L => RETURN [Ev[Boole.Eval[rls.first.rope, expr].whenFalse, rls.rest]];

ENDCASE => ERROR;

};

AlpsTest: RosemaryUser.TestProc = {

rexpr: Expression ← Decoder[];

abexpr: Expression ← And[Var["a"], Var["b"]];

FOR av: Ports.Level IN Ports.Level DO

p[a].l ← av;

FOR bv: Ports.Level IN Ports.Level DO

p[b].l ← bv;

FOR cv: Ports.Level IN Ports.Level DO

p[c].l ← cv;

FOR dv: Ports.Level IN Ports.Level DO

p[d].l ← dv;

p[r].l ← SELECT Ev[rexpr, LIST[["a", av], ["b", bv], ["c", cv], ["d", dv]]] FROM

Boole.true => H,

Boole.false => L,

ENDCASE => X;

p[ab].l ← SELECT Ev[abexpr, LIST[["a", av], ["b", bv], ["c", cv], ["d", dv]]] FROM

Boole.true => H,

Boole.false => L,

ENDCASE => X;

Eval[];

ENDLOOP;

};

ExerciseRose: PUBLIC PROC = {

ct: CellType ← DecoderCellType[];

public: Wire ← ct.public;

data: CoreClasses.RecordCellType ← NARROW [ct.data];

sim: Rosemary.Simulation;

design: PW.Design;

a ← CoreOps.GetWireIndex[public, "a"];

b ← CoreOps.GetWireIndex[public, "b"];

c ← CoreOps.GetWireIndex[public, "c"];

d ← CoreOps.GetWireIndex[public, "d"];

r ← CoreOps.GetWireIndex[public, "r"];

ab ← CoreOps.GetWireIndex[public, "ab"];

Gnd ← CoreOps.GetWireIndex[public, "Gnd"];

Vdd ← CoreOps.GetWireIndex[public, "Vdd"];

phiA ← CoreOps.GetWireIndex[public, "phiA"];

phiB ← CoreOps.GetWireIndex[public, "phiB"];

VRef ← CoreOps.GetWireIndex[public, "VRef"];

[] ← Rosemary.SetFixedWire[public[Vdd], H];

[] ← Rosemary.SetFixedWire[public[Gnd], L];

[] ← Rosemary.SetFixedWire[public[phiA], H];

[] ← Rosemary.SetFixedWire[public[phiB], H];

[] ← Rosemary.SetFixedWire[public[VRef], H];

FOR i: NAT IN [0..ct.public.size) DO

[] ← Ports.InitPort[wire: ct.public[i], initType: l];

ENDLOOP;

[] ← Ports.InitTesterDrive[wire: ct.public[a], initDrive: force];

[] ← Ports.InitTesterDrive[wire: ct.public[b], initDrive: force];

[] ← Ports.InitTesterDrive[wire: ct.public[c], initDrive: force];

[] ← Ports.InitTesterDrive[wire: ct.public[d], initDrive: force];

[] ← Ports.InitTesterDrive[wire: ct.public[r], initDrive: expect];

[] ← Ports.InitTesterDrive[wire: ct.public[ab], initDrive: expect];

sim ← RosemaryUser.TestProcedureViewer[name: "Alps Transistor Tester", cellType: ct, testButtons: LIST["AlpsTest"], displayWires: RosemaryUser.DisplayCellTypePortLeafWires[ct], flatten: TRUE];

design ← PW.Draw[PWCore.Layout[ct]];

CDProperties.PutDesignProp[design, $Simulation, sim];

[] ← RosemaryUser.TestProcedureViewer[name: "Alps Alps Tester", cellType: ct, testButtons: LIST["AlpsTest"], displayWires: RosemaryUser.DisplayCellTypePortLeafWires[ct], flatten: TRUE, cutSets: LIST["AlpsCell"]];

};

RosemaryUser.RegisterTestProc["AlpsTest", AlpsTest];

END.