[Cyan]<D0Source>Proms>Rev-L>PromDefs.Mc!1

%File PromDefs.mc
Edit by HGM March 8, 1980 1:58 PM

Add FatalRdcErrorLoc, shuffel page assignments to make it come out right.
Edit by HGM March 6, 1980 1:30 PM

Add some MPCodes, add/shuffel Rdc codes, delete RdcRetryCount,
Add EtherBootLoc
Edit by Jim Frandeen March 2, 1980 2:01 PM Assure Font 0
Edit by Jim Frandeen February 22, 1980 12:15 PM H4 parity errors for Model 31
Edit by HGM February 13, 1980 11:30 AM Shuffel MP codes
Edit by Jim Frandeen February 13, 1980 8:46 AM MPCode for disk not ready
Edit by Jim Frandeen February 13, 1980 8:46 AM MPCode for disk not ready
Edit by Jim Frandeen February 5, 1980 9:40 AM change btTemp to R3
Edit by HGM February 2, 1980 7:14 PM Switch EtherTasks
Edit by Jim Frandeen February 1, 1980 9:40 PM

Created by Jim Frandeen January 25, 1980t
%

Insert[D0Lang];

*CONDITIONAL ASSEMBLY DEFINITIONS

SET[Model31,0];*=1 if booting from the Model 31 disk; otherwise booting from the SA4000.

SET[MidasTesting,0];*=1 if testing in Midas. If Testing, don’t use page 0 Midas Locations and don’t clear Control Store.

SET[NotMidasTesting,XOR[1,MidasTesting]];

*TASK DEFINITIONS

SET[BootTask,0];

SET[Model31BootTask,0];

MC[RdcTaskNumber,4];

SET[OutTask,4];*Ether Output

SET[InTask,10];*Ether Input

MC[RdcTaskNumberComplement,13];

SET[RdcTask,RdcTaskNumber!];

*Tasks must have zero in the two low order bits; otherwise they will not be able to address their registers. This is because every R address has 11 in the low order two bits. In order to have 16 usable registers, the task must be able to reference 64 registers.

*PAGE DEFINITIONS

SET[InitializeRegisterPage,6];

SET[InitialBootPage,0];

* The first 100 words of 0ages 0 through 5 are protected: Initial can’t overlay them.

* That should get expanded to include pages 6+7 when Initial gets fixed.

SET[DiskBootPage,InitialBootPage];*Disk (Model 31 or SA4000) Resident Loader

SET[DiskBootPage1,5];*Disk (Model 31 or SA4000) Resident Loader

SET[DiskBootPage2,2];*Disk (Model 31 or SA4000) Resident Loader

SET[EmPage,3];*Resident Ethernet boot loader

SET[InPage,4];*Resident Ethernet boot loader

SET[OutPage,1];*Resident Ethernet boot loader

SET[DiskBootPage3,1];* SA4000 overflow

* Things are getting tight, it will get better when Initial gets fixed.

SET[TrapPage,DiskBootPage2];* Trap for unexpected Wakeups

* Pages 10 through 16 can be reused by Initial
SET[TestPage1,10];*Code can be loaded over
SET[TestPage2,11];*Code can be loaded over
SET[TestPage3,12];*Code can be loaded over
SET[MidasBootPage,13];*Code can be loaded over

SET[ZapPage,14];* Clear Timers, ZapDevices

SET[InitPage,14];* Device initialization

SET[SetPanelPage,InitialBootPage];

* Leave 17 empty for Midas and whatever

* Bolt things down so we can jump/notify from Initial if it gets in trouble

* Get here in Task 4 (RdcTask) with error number in RdcMPCode.
Set[FatalRdcErrorLoc, 462]; * That’s where it was in Rev I

* Get here in task 0 with error number in T and MP. All devices must be quiet.
Set[EtherBootLoc, 1400];

*MACRO DEFINITIONS

*Boot microcode is special since it is loaded from a ROM that is 32 bits wide, while control store is 36 bits wide. This means we lose four bits. The bits are: (1) RSEL4 and RSEL5 are forced to be ones. This means we can use only 16 R locations, and every R address has 11 in the low order two bits. (2) JA[0:1] must be 00. This means we can use only the first 64 locations of each page. The following macros force the correct value into the RSEL field. We must use Input@ and Output@ instead of Input and Output.

DEFAULT[IM, RX@[3] ];

MACRO[INPUT@, MRTYP@[IFG[#0,1,FF2@[#2]1707,1307]] RX@[3] MEMR0@[#1] ?];
MACRO[OUTPUT@,MRTYP@[IFG[#0,1,FF2@[#2]1713,1313]] RX@[3] MEMR0@[#1] ?];
*BootRegNumber and RdcRegNumber return an 8-bit register number with 11 in the low order two bits, given a number [0..17]. Example: 1 returns 33, 2 returns 7.

MACRO[BootRegNumber,ADD[LSHIFT[#1,2],LSHIFT[BootTask,4],3]];

MACRO[RdcRegNumber,ADD[LSHIFT[#1,2],LSHIFT[RdcTask,4],3]];

MACRO[BootReg,AND[77,BootRegNumber[#1]]];

MACRO[RdcReg,AND[77,RdcRegNumber[#1]]];

*BOOT TASK REGISTER DEFINITIONS

SET Task[BootTask];

RV[btTemp, BootReg[ 0]];*NOTE: This must be R3!

RV[btErrorCode, BootReg[ 1]];

RV[btWord0, BootReg[ 1]];*Used by Midas Loader and Model31Boot.

RV[btTemp1, BootReg[ 2]];

RV[btData, BootReg[ 3]];*Used only by Midas Loader

RV[btFinished, BootReg[ 3]];*Model31Boot: contains status mask for each seek/sector

RV[btByte, BootReg[ 4]];*Used only by Midas Loader. Flag for Receive: 0 for word, 1 for byte

RV[btDskAddr, BootReg[ 4]];*Model31Boot: holder of disk address

RV[btSlotCount, BootReg[ 4]];*Model31Boot recycled register: used in FindDisk

RV[btPIDstate, BootReg[ 5]];*Used only by routine that unscrambles processor ID.

RV[btDskTmp, BootReg[ 5]];*Model31Boot: general purpose

RV[btDeviceID, BootReg[ 5]];*Model31Boot recycled register: used in FindDisk

RV[btFatalErrors, BootReg[ 6]];*Model31Boot: error count gets decremented.

RV[btWord1, BootReg[ 7]];*Used only by Midas Loader.

RV[btChecksum, BootReg[ 7]];*Model31Boot: running checksum

RV[btParityReturn, BootReg[ 10]];*Address to notify if we are expecting H4 parity error; otherwise this register is zero. Must not be recycled.

RV[btCSAddr, BootReg[ 11]];

RV[btParityTemp, BootReg[ 12]];*Used by ParityError routine. Must not be recycled.

RV[btCount, BootReg[13]];

RV[btBits32To35, BootReg[14]];*Used only for stack initialize

RV[btDskStatus, BootReg[14]];*Model31Boot: holder of status

RV[btBits00To15, BootReg[15]];*Used only for stack initialize

RV[btState, BootReg[15]];*Model31Boot: reading header, label, data

RV[btBits16To31, BootReg[16]];*Used only for stack initialize

RV[btReadPtr, BootReg[16]];*Model31Boot: read pointer for disk

RV[btZeroRegAddr, BootReg[17]];*Used only for stack initialize

RV[btWhichWord, BootReg[17]];*Model31Boot: state holder for storeCS routine

*RDC TASK REGISTER DEFINITIONS

SET Task[RdcTask];

RV[RdcWord0, RdcReg[ 0]];*Used by LoadCS

RV[RdcControllerID, RdcReg[0]];*Used only for initialize RDC

RV[RdcWord1, RdcReg[1]];*Used by LoadCS

RV[RdcCount, RdcReg[1]];*Used only for initialize RDC

RV[RdcWord2, RdcReg[2]];*Used by LoadCS

RV[RdcChecksum, RdcReg[ 3]];*running checksum

RV[RdcRdcTask, RdcReg[3]];*Used only for initialize RDC

RV[RdcCSAddress, RdcReg[4]];*Used by LoadC

RV[RdcTemp, RdcReg[5]];*Used by LoadC

RV[RdcSectorTimeOutCount, RdcReg[6]];

RV[RdcWordCount, RdcReg[7]];*words to process each wakeup

RV[RdcCommand, RdcReg[10]];

RV[RdcMPCode, RdcReg[ 10]];

RV[RdcWakeupCount, RdcReg[10]];

RV[RdcDiskStatus, RdcReg[11]];

RV[RdcZero, RdcReg[12]];*Always contains zero

RV[RdcWord, RdcReg[ 13]];*word read from controller

RV[RdcWhichWord, RdcReg[ 14]];*Which CS word

RV[RdcHeadSettleCount, RdcReg[15]];

RV[RdcHeadSector, RdcReg[17]];*HeadSectorReg: NOTE: This register address (77) must not change. This is known to SA4000Loader. This is how we know where to read the next sector.

*ERROR CODES TO BE DISPLAYED IN THE MAINTENANCE PANEL

MC[MPCodeFaultHappened,24];*20-35 decimal (20+Pairity)

MC[MPCodeStartRdcBoot,50];*40 decimal SA4000

MC[MPCodeNoRdcController,51];*41 decimal SA4000

MC[MPCodeReadError,52];*42 decimal SA4000

MC[MPCodeSeekTimeOut,53];*43 decimal SA4000

MC[MPCodeChecksumError,54];*44 decimal SA4000

MC[MPCodeBadCSAddress,55];*45 decimal SA4000

MC[MPCodeDiskNotReady,56];*46 decimal SA4000

MC[MPCodeBadBootFile,57];*47 decimal SA4000

MC[MPCodeRdcTimeout,60];*48 decimal SA4000

MC[EtherMPCodeEtherbooting,74];*60 decimal Ether
MC[EtherMPCodeNoEthernet,75];*61 decimal
MC[EtherMPCodeChecksumError,76];*62 decimal
MC[EtherMPCodeBadCSAddress,77];*63 decimal
MC[EtherMPBadStatus,100];*64 decimal
MC[EtherMPTimeout,101];*65 decimal Ether

MC[MPCodeUnexpectedWakeup,106];*70-85 Decimal (70+CTask)

MC[MPCodeDataTimeOut,133];*91 decimal Model 31

MC[MPCodeCantFindDisk,134];*92 decimal Model 31

MC[MPCodeSectorTimeOut,135];*93 decimal Model 31

MC[MPCodeCheckSumIncorrect,136];*94 decimal Model 31

MC[MPCodeCantFindSector,137];*95 decimal Model 31

*CONSTANTS

SET[LastEPROMpage,5];*Last EPROM page that must not be loaded over.

SET[ScrambledProcessorIDAddress,7475];*Address where Processor ID is loaded into Control Store from the Prom.

SET[ProcessorIDaddress,7777];*Address where Processor ID is saved in Control Store.

*Reserve area in each page after EPROM area.

IMRESERVE[0,100,300];
IMRESERVE[1,100,300];
IMRESERVE[2,100,300];
IMRESERVE[3,100,300];
IMRESERVE[4,100,300];
IMRESERVE[5,100,300];
IMRESERVE[6,100,300];
IMRESERVE[7,100,300];
IMRESERVE[10,100,300];
IMRESERVE[11,100,300];
IMRESERVE[12,100,300];
IMRESERVE[13,100,300];
IMRESERVE[14,100,300];
IMRESERVE[15,100,300];
IMRESERVE[16,100,300];
IMRESERVE[17,100,300];

:END[PromDefs];