:TITLE[Mesa2Occupied];

%Ed Fiala 3 June 1983: For Tom Henning, when WithMidas=0, make 115b locations
on page 17b available to Pilot1 if WithEOM=1; make 225b locations
available to Pilot1 if With3MB=0 and WithEOM=1.
Tom Rich September 8, 1982: WithTor => WithEOM.
Ed Fiala 18 May 1982: Add 2 page 17b locations for Fault.Mc in Pilot1.
Ed Fiala 26 April 1982: Absorb CDC9730 reserve from Tom Rich.
Ed Fiala 2 April 1982: Eliminate IFDC stuff on page 17b; change Fault.Mc
reserve on page 17b; change for 10 mb Ethernet stuff; changes to make
reservations explicit except on pages 4-7; absorb IMReserve for MIOC
formerly in MIOC.Mc; detailed reserve on page 14.
Ed Fiala 8 October 1981: Allow for MidasPage in Fault.Mc; assign
almost all of page 0 to Pilot1 for Fault.Mc; give unused page 3 to Pilot2.
Ed Fiala 15 June 1981: Reduce Midas Kernel reserve.
Ed Fiala 27 April 1981: Add page 17 reserve to allow Pilot2 to use page 17;
changes for movement of XWTask, XWSio2, TextBlt, MesaFP; incorporate
LoadRAMOccupied here; fix for page 0 reserve.
Ed Fiala 20 March 1981: Add reserve for Initial’s timer task on page 11 for
Kernel’s on page 16 (as a comment), and for MesaFP on page 13.
Ron Joiner December 15, 1980 3:02 PM add reserve for textblt


Reserve ALL locations that must not be smashed by code in Pilot1. This
includes those occupied by Initial during LoadRAM or by Midas when debugging
and those locations reserved for Pilot2 (or subsequent overlays) that are on
pages where Pilot1 code will have to remain after initialization. Pages 4-7
are totally overwritten by Pilot2 and not reserved here; these may be used
for throwaway initialization in Pilot1, and, by convention, are the ONLY
pages currently used for throwaway initialization. Pages 4-7 may not be
used for anything that must remain after initialization.

On pages shared between Pilot1 and Pilot2, the union of IMReserve’s in the
occupied files is, by convention, 400b words, so unintentional overwriting
always produces an error, though sometimes a fictitious one which can be fixed
by moving some excess reserved locations between the Occupied files.

The fault handler in Pilot1 substitutes for that in Initial/Kernel, so the
corresponding locations in Initial/Kernel are not reserved here.
%

IMReserve[0,2,3];*For 3 mi in MesaOP2.Mc buffer refill + 1 mi after
IMReserve[0,10,3];*InitEnd in MesaOP3.Mc - 1 mi at Qloc (.eq. 5)
IMReserve[0,20,1];*InitEnd in Pilot2 MesaOP3, placed with At
IMReserve[0,300,40];*LoadRAM.Mc in Initial
IMReserve[0,370,2];*LoadRAM.Mc

*Page 1 is used by ENXTask, XWSIO2, CDC9730, EIM.
*Page 2 is used by EOMStarHiTask, MIOC, or Cedar.
*Page 3 is used by EOMStarLoTask or CDCTask, MesaIO, and Cedar

:IF[WithMIOC]; ***********************************
IMReserve[IOPage,0,235];*For MIOC overlays (MIOCBit, MIOCByte, MIOCAsync,
*or MIOCTTY); this code could be bummed a lot if
*necessary.
:ENDIF;*******************************************

:IF[WithCDC]; ************************************
IMReserve[3,0,222];*54b locations for CDCTask (2 extra)
IMReserve[3,300,100];*rest of page for Pilot2
:ELSEIF[WithEOM];*********************************
*Pilot1 gets whole page
:ELSE;********************************************
IMReserve[3,0,400];*For MesaIO, CedarGC, and ?
:ENDIF;*******************************************

:IF[WithCedar]; **********************************
IMReserve[2,0,400];*For CedarGC.Mc
:ENDIF;*******************************************

IMReserve[10,0,400];*For MesaESC, MesaFP dispatch, CedarGC dispatch,
*etc.

IMReserve[11,0,400];*Initial’s timer task code and Pilot2’s BitBlt.Mc.
*Initial could be changed so that only a few
*locations had to be reserved.

*Page 12 is for the UTVFC or UIB display driver in Pilot1.

:UNLESS[WithCDC9730]; ****************************
IMReserve[13,0,400];*For MesaFP or whatever
:ENDIF;*******************************************

*Page 14 is for RDC and Timer primarily, but Pilot2 can overwrite the
*unused TimerTable entries and unused space.
IMReserve[14,367,11];*Pilot2 will overwrite any unused TimerTable
*entries (not IMReserved here because they are
*initialized to cause a crash).

IMReserve[15,0,400];*xfPage1 for MesaOP3.Mc, etc.

IMReserve[16,0,400];*MesaP.Mc
:IF[WithMidas]; **********************************
*IMReserve[16,1,14];*Midas Kernel timer task code (unnecessary to
*reserve this here so long as Initial is loaded
*ahead of Pilot1).
:ENDIF; ******************************************

%The current policy for page 17 allocation is as follows:
If WithMidas=1, 33b locations are given to Pilot1 for MidasPage in Fault.Mc,
and 117b locations are reserved for the Midas Kernel; elseif WithEOM=1, these
locations are given to Pilot1; else they are given to Pilot2. An additional
225b locations are given to the 3mb Ethernet, the EOM, or Pilot2.
%
:IF[WithMidas]; **********************************
IMReserve[17,1,2];*Midas Kernel resident
IMReserve[17,4,74];*Kernel resident
IMReserve[17,100,20];*Kernel overlays
IMReserve[17,120,1];*Kernel resident
:UNLESS[With3MB]; ******************************
IMReserve[17,152,225];*Only 206b of the 225b locations are used
:ENDIF;*****************************************
:ELSEIF[WithEOM]; ********************************
:ELSE; *******************************************
IMReserve[17,1,2];*Unused locations given to Pilot2 (Same as
IMReserve[17,4,115];*Kernel reserve, plus 33b locations that would
IMReserve[17,0,1];*be occupied by MidasPage in Fault.Mc)
IMReserve[17,3,1];
IMReserve[17,121,31];
:UNLESS[With3MB]; ******************************
IMReserve[17,152,225];*Only 206b of the 225b locations are used
:ENDIF;*****************************************
:ENDIF; ******************************************
IMReserve[17,377,1];*7777b unusable with LoadRAM; contains the machine
*number setup by the Boot microcode and read by
*software using ReadRAM.

:END[Mesa2Occupied];