:TITLE[Mesa1Occupied];

%Ed Fiala 30 May 1984: Change page 14b IMReserve for Blackman.
Ed Fiala 3 November 1983: Fix IMReserve on page 14b.
Ed Fiala 24 May 1983: Fix IMReserve on page 17b when WithEOM=1.
Tom Rich September 8, 1982: WithTor => WithUIB and WithEOM.
Ed Fiala 18 May 1982: Page 17 reserve changed for Fault.Mc.
Ed Fiala 26 April 1982: Absorb edit from Tom Rich for ESS configuration.
Ed Fiala 2 April 1982: Eliminate IFDC on page 17b; change Fault.Mc reserve
  on page 17b; change for 10 mb Ethernet and WithMIOC; use WithTOR for EOM;
  partition page 14; 3 mb Ethernet to page 17b.
Ed Fiala 8 October 1981: Allow for MidasPage in Fault.Mc; move TimerPage from
  0 to 14, FaultPage1 from 14 to 0, assign most of page 0 to Pilot1; give
  unused page3 to Pilot2; move CDCTask to page 14.
Ed Fiala 15 June 1981: Reduce reservation for new Midas Kernel.
Ed Fiala 29 April 1981: Elim page 17 KeyTable reserve, change IFDC reserve;
  changes for movement of XWTask, XWSio2, MesaFP, TextBlt; reserve more of
  page 0 for Pilot1; CedarMode and WithMidas conditionals; provision for
  overwriting TimerTable by Audio.Mc and Jasmine.Mc.
Ed Fiala 20 March 1981: Fix page 13 reserve.
Ev Neely  February 9, 1981  7:48 PM change Fault reserve


Reserve ALL locations that Pilot2 must not smash.  These include those
occupied by Pilot1, Initial/Kernel, or overlays loaded after Pilot2.

On all pages except 4-7 (throwaway initialization pages in Pilot1), the
union of IMReserve's in Mesa1Occupied.Mc and Mesa2Occupied.Mc covers all
400b words, so unintentional overwriting always produces an error, though
sometimes a fictitious one fixable by moving excess reserved locations
between Occupied files.  Also, the sum of the IMReserves in the two
Occupied files will be 400b on all pages except 4-7 and the following:

1) On page 0, Qloc in Pilot1 Initialize.Mc is legitimately overwritten and
42b mi are reserved in both Occupied files for LoadRAM, inherited from
Initial (so the sum of IMReserved words on page 0 should be 400b less 1
for Qloc + 42b for LoadRAM or 441b words).

2) On page 14b, the Timer page, unused timer dispatch table entries are
initialized to crash in Pilot1, but are not IMReserved, so they may be
legitimately overwritten by Pilot2.

3) On page 17b, word 377b is unusable due to a MicroD restriction, so it is
IMReserved in both Occupied files.  Also, if WithMidas is true, 117b
locations are IMReserved in both Occupied files for Kernel.  So the sum of
IMReserved words is 401b words if WithMidas=0, 520b if WithMidas=1.
%

*2-4 and 20-22 for Pilot2, 5 legitimately overwritten, rest of page for
*Pilot1 and LoadRAM.
IMReserve[0,0,2];		*Fault and Initialize
IMReserve[0,6,12];	*(Qloc=5 legitimately overwritten)
IMReserve[0,23,355];

IMReserve[1,0,400];	*ENXTask, CDCTask, XWSIO2, CDC9730, EIM

:IF[WithEOM]; ************************************
  IMReserve[eomHiTaskPage,0,400];	*EOMHiTask
  IMReserve[eomLoTaskPage,0,400];	*EOMLoTask
:ENDIF;*******************************************

:IF[WithUIB]; ************************************
  IMReserve[uibPage,0,400];		*UIB (TOR display)
:ELSE;********************************************
  IMReserve[DisplayPage,0,400];	*Display page for LF, CSL, or CSLF config
:ENDIF;*******************************************

:IF[WithCDC]; ************************************
  IMReserve[3,222,56];	*CDCTask
:ENDIF;*******************************************

:IF[WithMIOC]; ***********************************
  IMReserve[IOPage,0,400];	*Reserve for MIOC and variants in overlays.
:ENDIF;*******************************************

:IF[WithCDC9730]; ******************************
  IMReserve[vdPage,0,400];	*CDC 9730 Disk on page 13 (and page 1)
:ENDIF;*******************************************

*RDC, Timer write 317b+35b=354b locations leaving 24b free; in addition
*unused TimerTable locations can be overwritten by Pilot2.  The locations
*given to Pilot1 must include MidasHaltLoc (213b and several around 213b),
*and StartIOLoc (140b).
IMReserve[14,0,332];
IMReserve[14,335,2];	*TimerGoLoc & TimerGoLoc+1
*Allow Pilot2 to overwrite TimerTable entries unused by Pilot1.
IMReserve[14,340,2];	*Refresh timer & user timer
:IF[With10MB]; ***********************************
  IMReserve[14,Add[340,Xor[17,enxTask]],1];	*1st 10 mb Ethernet timer slot
  IMReserve[14,Add[340,Xor[17,enxTask2]],1];	*2nd 10 mb Ethernet timer slot
  IMReserve[14,Add[340,Xor[17,enxTask3]],1];	*3rd 10 mb Ethernet timer slot
:ENDIF;*******************************************
:IF[With3MB]; ************************************
  IMReserve[14,Add[340,Xor[17,xoTask]],1];	*1st 03 mb Ethernet timer slot
  IMReserve[14,Add[340,Xor[17,xoTask2]],1];	*2nd 03 mb Ethernet timer slot
:ENDIF;*******************************************
IMReserve[14,360,20];

%The current policy for page 17 allocation is as follows:
If WithMidas=1, 33b locations are given to Pilot1 for MidasPage in Fault.Mc,
and 117b locations are reserved for the Midas Kernel; otherwise, these
locations are given to Pilot2.
%
:IF[WithMidas]; **********************************
  *IMReserve[16,1,14];	*Midas Kernel timer task--reserve not needed
			*because Pilot1/Cedar1 timer task is running when
			*Pilot2/Cedar2 is loaded.

  IMReserve[17,1,2];	*Midas Kernel resident
  IMReserve[17,4,74];	*Kernel resident
  IMReserve[17,100,20];	*Kernel overlays
  IMReserve[17,120,1];	*Kernel resident
  IMReserve[17,0,1];	*33b locations for MidasPage in Fault.Mc
  IMReserve[17,3,1];
  IMReserve[17,121,31];
:ELSEIF[WithEOM]; ********************************
  IMReserve[17,0,152];
:ENDIF; ******************************************
:IF[With3MB]; ************************************
  IMReserve[17,152,225];	*Only 206b of the 225b locations are used
:ENDIF;*******************************************
IMReserve[17,377,1];	*7777b unusable with LoadRAM; contains the
			*machine number setup by the Boot microcode;
			*this is read by software using ReadRAM.

:END[Mesa1Occupied];
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