:TITLE[Mesa1Occupied];

%Edit by Fiala 18 March 1982: Eliminate IFDC on page 17b; change Fault.Mc
  reserve on page 17b; change for 10 mb Ethernet and WithMIOC; use WithTOR
  for EOM.
Edit by Fiala 8 October 1981: Allow for MidasPage in Fault.Mc; move
  TimerPage from 0 to 14, FaultPage1 from 14 to 0, assign most of page 0
  to Pilot1; give unused page3 to Pilot2; move CDCTask to page 14.
Edit by Fiala 15 June 1981: Reduce reservation for new Midas Kernel.
Edit by Fiala 29 April 1981: Elim page 17 KeyTable reserve, change IFDC
reserve; changes for movement of XWTask, XWSio2, MesaFP, TextBlt; reserve
more of page 0 for Pilot1; CedarMode and WithMidas conditionals; provision
for overwriting TimerTable by Audio.Mc and Jasmine.Mc.
Edit by Fiala 20 March 1981: Fix page 13 reserve.
Edit by Neely  February 9, 1981  7:48 PM change Fault reserve


Reserve ALL locations that Pilot2 must not smash.  These include those
occupied by Pilot1, Initial/Kernel, or overlays loaded after Pilot2.

On all pages except 4-7 (throwaway initialization pages in Pilot1), the union
of IMReserve's in Mesa1Occupied.Mc and Mesa2Occupied.Mc covers all 400b words,
wso unintentional overwriting always produces an error, though sometimes a
fictitious one fixable by moving some excess reserved locations between the
Occupied files.  Also, the sum of the IMReserves in the two Occupied files
will be 400b on all pages except 4-7 and the following:
1) On page 0, Qloc in Pilot1 Initialize.Mc is legitimately overwritten and
42b mi are reserved in both Occupied files for LoadRAM, inherited from
Initial (so the sum of IMReserved words on page 0 should be 400b less 1
for Qloc + 42b for LoadRAM or 441b words).
2) On page 17b, word 377b is unusable due to a MicroD restriction, so it is
IMReserved in both Occupied files.  Also, if WithMidas is true, 117b
locations are IMReserved in both Occupied files for Kernel.  So the sum of
IMReserved words is 401b words if WithMidas=0, 520b if WithMidas=1.
3) On page 14b, the Timer page, unused timer dispatch table entries are
initialized to crash in Pilot1, but are not IMReserved, so they may be
legitimately overwritten by Pilot2.

NOTES:
1) If the With3MB conditional starts being set to 0, its page 14b reserve will
need to be split off from the rest.
%

IMReserve[0,0,2];	*Fault
IMReserve[0,6,2];	*Initialize (Qloc+1; Qloc legitimately overwritten)
			*PFExit in Fault.Mc (absolutely placed).
IMReserve[0,13,5];	*PNIP, NotifyInterrupt, Fault, LRJ, etc.
IMReserve[0,21,357];	*PNIP, NotifyInterrupt, Fault, LRJ, etc.

:IF[With10MB]; ***********************************
IMReserve[1,0,400];	*Formerly ???Reserve for RS232 stuff???
			*Now Reserve for 10 mb Ethernet driver
IMReserve[14,Add[340,Xor[17,enxTask]],1];	*1st 10 mb Ethernet timer slot
IMReserve[14,Add[340,Xor[17,enxTask2]],1];	*2nd 10 mb Ethernet timer slot
IMReserve[14,Add[340,Xor[17,enxTask3]],1];	*3rd 10 mb Ethernet timer slot
:ENDIF;*******************************************

:IF[WithTOR]; ***********************************
IMReserve[1,0,400];	*Reserve for EOMLoTask.
IMReserve[2,0,400];	*Reserve for EOMHiTask.
:ENDIF;*******************************************

:IF[WithMIOC]; ***********************************
IMReserve[2,0,400];	*Reserve for MIOC controller and variants.
:ENDIF;*******************************************

IMReserve[12,0,400];	*Display page for LF, CSL, CSLF, or UIB config

IMReserve[13,0,400];	*RDC, XWSio2

*Allow TimerTable entries unused by Pilot1 and 20b locations at the end of
*TimerPage to be overwritten by Pilot2.
IMReserve[14,0,341];	*XWTask (3 mb), CDCTask, Timer
:IF[With3MB]; ************************************
IMReserve[14,Add[340,Xor[17,xoTask]],1];	*1st 03 mb Ethernet timer slot
IMReserve[14,Add[340,Xor[17,xoTask2]],1];	*2nd 03 mb Ethernet timer slot
:ENDIF;*******************************************

%The current policy for page 17 allocation is as follows:
If WithMidas=1, 31b locations are given to Pilot1 for MidasPage in Fault.Mc,
and 117b locations are reserved for the Midas Kernel; otherwise, these
locations are given to Pilot2.
%
:IF[WithMidas]; **********************************
*IMReserve[16,1,14];	*Midas Kernel timer task--reserve not needed
			*because Pilot1/Cedar1 timer task is running when
			*Pilot2/Cedar2 is loaded.

IMReserve[17,1,2];	*Midas Kernel resident
IMReserve[17,4,74];	*Kernel resident
IMReserve[17,100,20];	*Kernel overlays
IMReserve[17,120,1];	*Kernel resident
IMReserve[17,0,1];	*31b locations for MidasPage in Fault.Mc
IMReserve[17,3,1];
IMReserve[17,121,27];
:ENDIF; ******************************************
IMReserve[17,377,1];	*7777b unusable with LRJ (?)

:END[Mesa1Occupied];
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