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CameronGcPPPPIdata.00Idata.01Idata.02Idata.03Idata.04Idata.05Idata.06Idata.0718317917776Q7Q6Q5Q4D7D6D5D4TTTTSD3D2D1RRRRRRRRD0TTTTQ0Q1Q2Q3SCKOC'PPP193191189187PS374EdgeClk1'Idata Mux Register/Parity GenPPPPPPPPIdata.08Idata.09Idata.10Idata.11Idata.12Idata.14Idata.15165164162161159158157Idata.13153EdgeClk1'S374Q7Q6Q5Q4D7D6D5D4TTTTSD3D2D1RRRRRRRRD0TTTTQ0Q1Q2Q3SCKOC'S1S2STTRRRRRRRRRROYOXY3Y2Y1Y0X3X2X1X0SEY'EX'PS253Idata.1614816543101112132147915TestGrpParIMeF'.IMux.08IMux.09IMux.10IMux.11IMux.12IMux.13IMux.14IMux.15RRRRRRRRRODDTTEVNS280BufIdataPar.....RdErrBufErrWriteFaultSeekCompSTrack00SDevSelOKOFaultFi19f19e18ABTRRiIMeFIaddr.4'S00546dStatusParStatusPari16Sector00S2/6/79* Testability control to be added for etch module.h18b.RdErrBufErrWriteFaultSeekCompSTrack00SDevSelOKIMux.08IMux.09IMux.10IMux.11IMux.12IMux.13IMux.14IMux.15OFaultFGNDSector00SGNDQ3Q2Q1Q0TTTTD0RRRRRRRRB0D1B1D2B2D3B3SSBE'SS257Iaddr.7'Iaddr.7'S257Q3Q2Q1Q0TTTTD0RRRRRRRRB0D1B1D2B2D3B3SSBE'SGNDf9e91511314101165324791215113141011653247912Hi2Hi2Hi2RDC16.sil16GNDGNDGNDGNDGNDGNDGNDGNDRateErrorIaddr.7'TDCRRS32a14cRateErrorIaddr.6'Iaddr.7'ServiceLateCDQ'QQSRTTRR'S'StatusPar.Hi2Hi2EdgeClk4'S74f6b1189121310ServiceLate'WakeRequestIdata.12CG -G G G  :tT W%UVVkkkkkO29;@9;C9;EP9;G3<%1P?1P@1PA1PC2D42EP2Fm2G9;Fm9;D49;A9;?6 <%9;W9;YQ9;[9;]3R_1PU1PW1PX51PYQ2Zn2[2\2]9;\9;Zn9;X59;U6 R_IxIXGU9@pAGU>;GU1sGU&WGU GUGUGMGMGAx>29&p]MG2@ ?W@MGMGF|YFRFOFM?tb5?_?]?[?X5?U?S?QGWGUmGS4GP7%Um7%V7%W7%X3eUm3eV3eW3eX8|S!8UZ8W8Y4O=3etY3eZ3e\2|R2S!2T=2UZ2Vv2W2X2Y3S|$ ]3S|$8S$ 93_$3et]58|X8Vv8T=8R7%t]57%\7%Z7%Y6|O=3tS6tS;ta $8\_$<\_$y<_ $=[C$]=]|$>Z&$@>[C$8Y $>X$>W$8W$=U$8V$GtaG_nG]5GZF|T=4;t^Q*:QC $*Q ;t]$r(]| $(\_ $(Z& $([C $(V $(W $(Y $p@F|EFHFCFAYF;F>F9F7Y?tK?I?G?EP?A?=?;PGKmGI4GFGDGAmG?4G<??G:*:B$*:A$*:?{$*:@$*:E $*:C$*:F&$*:GB$;tGf$r*;P *:; $4;H4;-$98E $8C$8GB$=?$9<=f$U;t; $;t;-$r8?{$<=B $8@$=?{$8A$8B$=GB$=E $]2? 2@=2AY2Bv2C3=B$ ]3=B$8=f$ 93I{$3etF8|Bv8@=8>8;7%tF7%E7%D7%C6|93t=6t=>C$@>E $>A$>A$3",3#l7l|8#8*22 2"<2#X2$u2%2'2(2*2+ 7t',7-l3%3&3'3(3+33,P3-l3.3B!$8!$3B/$4|6t!33!33B $*:-$*:#$*:"$F|*5Wt*?-G-l8- $3B2%/2%-2%,2%+1s)1s(l1s'O1s&32%#1s"9;-9;'5*:A $4;e$*- *7|*tG*Fm*EP*D4*C*A*@*?|;Xtt9$ @9$$ 9$|t] $A $9 $9$ $ $z $ $ $ $*:,$V*/ 8|#2"<2#X2$u2%9tk99O 9 99924T4>5(l|66#5 e6<e4#5 #8r$s9]$s7]$t:47#7l7:4$9 *:. $*, (8$:78$rO9 Ap@.x2 :t8|4Qf$97O-$r(O $9t.909,P F I4DJHFmD403-+)9*JQKm >CEGJ-|@=BvDFtJM_$AI$ 9A&$A&$ ]|GvFYE=D CA@?tIHGFmEPD4C2|<tAmAmk|<tK:J9$:H_9$:F&9$:C9$K& $J $G $H $D{ $C_ $E $F $V?$?{ ]$=$U=$?9%#%$#H$U$ ]$$$, $* $( $) $.A $-% $/^ $0z $)A9$+z9$-9$/9$V1P(+-I/|%'*,<]t032$&$ 9&z$&z$ ]|,+*)u(X'<&%]t/]-],]+]*])](l|"<2t&&|"<9t#lBr'r%^%^H(H*H+3H,P-l./03033-3+3)@ ]@ CDEFkHkI4kJQkKmJHFmD49-l9+39('sp@ K@(tZn([(\(](YQHEC*:+z$V $W T%|R!VS!VS!S!!P%:U $%:tTQ"sUmT$9 *#*"(X5 &W$&Wy$)$&W]U$&&(('|' t%)) %;'t'dA$) r$,s )| (]$]( $9$ yy$%:t%: $2 $U$&&$2*:*:$&W&(W 9/ *+.GNb *12141618234567891917151312011101214161823456789191715131201110121416182345678919171513120111012141618234567891917151312011101201110120111012011101214161823456789191715131201110191817161514131292468357191817161514131292468357191817161514131292468357PageEODD0DateRevDesignerProjectFileXEROXJ. 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CameronGcSectorMark'+ReadData-ReadData+PLOClock-PLOClock+WriteData-WriteData+WriteClock-WriteClockReady'Track00'SeekComplete'WriteFault'..GNDGNDGNDCGnd1CGnd2CGnd3SPLAT ASPLAT BSPLAT Cd1e1f1Index'VCCVCC17RDC17.sil........Splats, Spare PositionsP9P11P12P13P14P15P16P8P7P6P5P4P3P2P1TTTTRRRRRRRRTTTTRTTRP10P20P19P18P17FPLATVCCGND....GNDVCCP9P11P12P13P14P15P16P8P7P6P5P4P3P2P1TTTTRRRRRRRRTTTTRTTRP10P20P19P18P17FPLAT..GNDVCCP9P11P12P13P14P15P16P8P7P6P5P4P3P2P1TTTTRRRRRRRRTTTTRTTRP10P20P19P18P17FPLAT..GNDVCCP9P11P12P13P14P15P16P8P7P6P5P4P3P2P1TTTTRRRRRRRRTTTTRTTRP10P20P19P18P17FPLAT................Note: Splats A,B, and C are 16 pin platforms centered in the 20-pin pattern..................GNDVCCP9P11P12P13P14P15P16P8P7P6P5P4P3P2P1TTTTRRRRRRRRTTTTRTTRP10P20P19P18P17FPLAT..................GNDVCCP9P11P12P13P14P15P16P8P7P6P5P4P3P2P1TTTTRRRRRRRRTTTTRTTRP10P20P19P18P17FPLATP9P11P12P13P14P15P16P8P7P6P5P4P3P2P1TTTTRRRRRRRRTTTTRTTRP10P20P19P18P17FPLATVCCGND....................................GNDVCCP9P11P12P13P14P15P16P8P7P6P5P4P3P2P1TTTTRRRRRRRRTTTTRTTRP10P20P19P18P17FPLATg3e17b10c10h97/20/80Spare Positions (5):CG -G G G 9t9939k2%2%k2%O2%32%2%2%2%99O992%991%2%k%%kO2%%%%O%%2222O k O 3     2k2322 22 $%#%&3%(l%*+*)(l'O&3%#%+%)%'O%%,%,%""#%D4*D4*:4":4#%S*S*I"I"d*d*Z"Z2#2&32(l2* + * ) (l 'O &3 % #2+2)2'O2% ,2,2" $"*C*A*@*?*>*=*#;GU1sGU&WGU GUGUGMGMGAx>29&p]MG2@ >@tN4 : -> := -= >^ $=B $; $<% $*:<% $$*:; $$*:=B $$*:>^ $$\ $$K @$_' $$M @$Pm]5K _n *:|;#;)^ $.[$9/t\)[V$*:R_V$*:JV$0WJ/:J$*:QC$-K$*K]$*:O $*:L$!L9$!V^ 9$!V[9$!J9$P& @$R_ @$-]$9!QC9$*:@V$0W@/:@$9*:B$*:A$B $A $@ $:C:A:@)\U$ p_' M >^%t]5&WK&W#X!)_)])[v)Y>#a)a)W#W#tZ&'sdJ'sc 'sb's`$eC)d$*:|E#O*:S|$tI+SI{$$$eJ (I(J-(KJ(Lf(M(N$eK&$eLB$eM_$eN{$eO$eP$eQ$eR*:|F*:I!*:KZ*:M#U&@$*:G$ V#Gd$#G$ y#N#M#Lv#KZ#J=#I!#H#F*:N*:Lv*:J=*:H#O*:O*:E#E$etH(S(Q(P(O%^T *:|6<#@=*:C$t:4+D49$$$e:{(9(:(;(<(=(?$e;$e<$e=$e>$e@ $eA&$eBB$eC_*:|7Y*:9*:;*:>#E@$*:8e$ V#8Bd$#8B$ y#? #>#<#;#:#9#8u#7Y*:? *:<*::*:8u#@=*:@=*:6<#6<$et9^(C(BB(AI(@-%^D{ |' & % $u #X "< ! '&%$u#X"<!  rp4^L$| $!$"<$#X$$u$%$&$'s s!s"<s#Xs$us%s&s'$s($,$t"&W,"$$#%"s","s#H"s$e"s%"s&"s'$A%^&z'()*, $| $"<$$u$&l.A@$$!$ Vl d$l $ y'&%$u#X"<! $'$%$#X$!($($t""s,,"s*"s)"s(-%| ;Xt      ; X t  A$trA$$ +Hd   $ A ] z  | X @$$ V d$ $ y t X ;      t;     t ]"sd"s"s"s"s"sy$A$|;$t$$lz@$$H$ Vl$d$l$$ ytX;$$$$X$$  tA"sd"s$"s+"s]$$&W$$s|$ sssssstsXs;$$$$$$t$X$;9;9;9;9;9;;9;X9;t9;22222;2X2t29; 29;]$.t:.]$$3e777+7H7d73e3e$3eA3e]3ez3e3e3e9;|9;9;;9;t2@$9;$ V2d$2$ y22t2X2;22229;9;X9;9;29;9; 2 3et77774^ (l5W : V*:P&$*:M$ (lAp@ r0z}GNf< PageEODD0DateRevDesignerProjectFileXEROXJ. F. CameronRDC Logic ChangesRDCChanges.sil18Changed DevSelOK counter load control so that Dr/HdRegLd loads counteronly if DrSel[0:1] is changed.Added Seek counter at b9 to produce seek Step pulse when DevOpReg isLog. Dwg. p. 10.Log. Dwg. p. 14.Log. Dwg. p. 2, 3, 4, 5, & 15.loaded with Seek bit (OutD.05). Causes SeqAdr[0:3] to be 0000 when Seekis true. Inhibits Wake-up until Step has been generated.Replaced S189 (16 word) buffer with F93422 (256 word) buffer.Log. Dwg. p. 7 & 8.Log. Dwg. p. 3 & 13.Numerous minor changes in mechanization as a result of above.Log. Dwg. p. all.Deleted Wake PROM and Counter; removed XferLate from IOAttn; deleted Flow ControlCounter; added Data Wake up/down counter; added 3 wakw count to IOAttn.Deleted DRConnect signals and IDWord parity gen.Log. Dwg. p. 14 & 16.Added ability to load DevBufAdrReg & MemBufAdrReg from processor.Log. Dwg. p. 6 & 7.Removed cross wire of MemBufAdrReg Clear and SectorWakeS strings.Disabled Seek Counter at max count.Log. Dwg. p. 12Log. Dwg. p. 7.Log. Dwg. p. 4.Rev A:Initial ReleaseRev B:Added SyncTime to Timing Generator PROM address input.Changed reset of Op Register from Reset' to RstAbrt/Err'.Log. Dwg. p. 4.Added RateError FF.Log. Dwg. p. 3.Added DataReq to hold term for WakeReqF to override IOStrobe reset.Added term to Wake Counter enable to prevent incrementing beyond max, ordecrementing below 0.Log. Dwg. p. 3.Log. Dwg. p. 3.Set SectorMarkSP with SectorMarkSD.Adds RateError to Status Parity Generator.Changes DecClkEnable counter clock to DevClkSource'.Adds SectorMarkI'.Fixes Testability control.Fixes Idata Parity select.Removes 25S09s from BufAdrReg. Replaces them with s257s.Changes RateError qualifier to DataWrt.Rev C:Changed I/O connections to device to reflect etch version with multiple drives.Made SequenceEnd' true last byte time of SequenceEnd only. Added S00 at b6.Log. Dwg. p. 5.Log. Dwg. p. 16.Inverted Sync pattern.Log. Dwg. p. 9.Log. Dwg. p. 13.Log. Dwg. p. 14.Log. Dwg. p. 5.Log. Dwg. p. 16.Log. Dwg. p. 7.Log. Dwg. p. 3.Log. Dwg. p. 14.Moved S280 from i14 to i15.Log. Dwg. p. 15Added one clock delay and DevClk synchronization to parity error logic.Log. Dwg. p. 10.Deleted Abort from Wake Request logic.Log. Dwg. p. 3.Changed BufSeqAdr clock qualifier to SeqAdrXferS.Log. Dwg. p. 6.Devided load on DevClk'.Log. Dwg. various.Added TestMode' qualifier to DevSelOK to prevent writing on device in Test Mode.Log. Dwg. p. 13.Revised DataXferS logic.Log. Dwg. p. 6.Added PrimeIData to BufAdrReg Select.Log. Dwg. p. 6 & 7.Added Write Fault Clear FF.Log. Dwg. p. 2."Or'ed VerifyLabel with ReadLabel at Op Reg input.Log. Dwg. p. 4.Qualified BufSeqAdr Register Clock wiht (IMeF+OMeF)'.Log. Dwg. p. 6.Changed data error check to look at Syndrome.00 during ECCCheck.Log. Dwg. p. 11.Changed DevBufAdrReg clear term from SectorWakeS' to ClrDevOpS'. SectorWake clearedtoo soon. Changed SectorWakeS' to SectorWakeS.Log. Dwg. p. 3, 5, 7, & 12.Rev D:Added direct set of MyStrobeF by AllowWake to insure Wake-up inhibit.Log. Dwg. p. 2.Removed Reset from S174 @ d4 to prevent "glitch" of Sector00.Log. Dwg. p. 5.Changed reset of XferDataS FF to SequenceEnd'.Log. Dwg. p. 6.Changed latch of NonComp FF to insure at least 2 DevClk times on.Log. Dwg. p. 9.Revised serial parity check/gen logic control.Log. Dwg. p. 10.Added SectorMarkSP "and" ReadGate to Abort set term to indicate missing Sync pattern.Log. Dwg. p. 12.Reversed phase of PLO Clock to increase margin of strobe on read.Log. Dwg. p. 14.Rev E:Changed CRC control from DataTime to ECCShift.Log. Dwg. p. 11.Added detection for ServiceLate to indicate Header and Label data not loaded into buffer by Header SyncFound.ServiceLate added as Idata.05 in Status word.Log. Dwg. p. 12 & 16.Changes Reset functions from single Output function with data specified operations to specific Output functionsfor General Reset and Error Reset to eliminate gate noise on direct reset lines.Log. Dwg. p. 2.Added SeqAdrXferS' to BufSeqEnbl to insure transfer of Sequence Address even if IMeF or OMeF is true.Log. Dwg. P. 6 & 7.Deleted MemUsesBuf and PrimeIData from Buffer Control Sequencer to allow firmware control of MemBufAdrReg.Log. Dwg. p. 6 & 7.Added sychronization of Abort with DevClk (AbortSD) to prevent erroneous setting of Sequencer Address Registers.Added RateErrPossible to Buffer Control Sequencer to define actual time when rateerror can occur. DecreasedRateError wake-up count from 3 to 2 to insure RateError detection if delay in memory pipe and only 20 wordsinitially loaded in RDC buffer.Log. Dwg. p. 3 & 6.Log. Dwg. p. 4 & 12.Replaced Hi in Status Word with ServiceLate' in order to maintain correct parity.Log. Dwg. p. 12 & 16.Log. Dwg. p. 2, 6, & 7.REQUIRES REV B PROMS!!!Rev F:Changed AllowWake and WakeReqF control to allow firmware control of AlowWake. Added WakeRequest to IDWordbit 12 for firmware test. This is to facilitate "booting" from the disk.Log. Dwg. p. 2, 3, 4, & 16.Added PrimeIData output function to MemUsesBuf to allow firmware to Prime Idata without parity errorDeleted DevBufAdrLd output function.4/11/79Rev G:Changed AllowWake so that Odata.04 = 1 sets AllowWake to comply with unpublished convention of setting outputregisters to zero causing initialization of controllers.Log. Dwg. p. 4.GaRev Ga: generated from Rev G on 4/11/79 by CPT.1) Redrew splats at d1, e1, f1 as FPLATS to avoid ROUTE trace cuts (pg 17).2) Added spare positions at g3, h9, i9, e17, b10, c10 (pg 17).CG -G G G IxIXGU9@pAGU>;GU1sGU&WGU GUGUGMGMGAx>29&p]MG2@ @&@K@tcQFVb5aD'sdnb5)^V_HV^9]=,s]2[X5=+WX5\Q[GZn0#ZnYQA.YQTAS#U/:TSffdndn6R9(RQVQPmCOQHN4:N4/:PmU#M*J4IHGFm9EP'UD4OCL5WC :MKK%JIHG*:FmEP4;D4AVA?G/?>&s>p@t 09 kK9>wGNgYPageEODD0DateRevDesignerProjectFileXEROXJ. F. CameronRDC Logic Changes18Rev Ga: generated from Rev G on 4/11/79 by CPT.1) Redrew splats at d1, e1, f1 as FPLATS to avoid ROUTE trace cuts (pg 17).2) Added spare positions at g3, h9, i9, e17, b10, c10 (pg 17).RDCChanges2.silRev Gb: 9/3/79 - CPT1) Lift the following pins:a15.12c16.9d10.6i13.10a13.152) Add an S174 IC in position i9, and wire i9.16 to Vcc.3) Add the following wires:This change is a manual addition to the revision Ga MultiWire board.a15.12 to i16.9 (DevSelOK, pg 2,16)c16.9 to a15.11 (RstAbrt/Err', pg 3,2)d10.6 to a15.9 (ClrDevOpS', pg 12)a15.8 to h13.1 (ClrOp', pg 4,7 - new signal name)a15.10 to a15.5 (IRun, pg2,12)i13.10 to 19.4 (Unnamed signal - was InhHdrAbrt, pg 4)h13.7 to i9.3 (Unnamed signal - was VerifyLabel, pg 4)i11.9 to i9.9 (OpRegClk', pg 4)i11.1 to i9.1 (RstAbrt/Err', pg 4)i9.5 to a13.1 (InhHdrAbrt, pg 4,12)i9.2 to a13.15 (VerifyLabel, pg 4,12)Gc7/19/80Rev Gc: 7/18/80 (Multiwire) - CPT:1) Formed signal NewSeek (pg 4), and made old Seek signal =0 so that the format sequencer will treat seek as a nop.2) Changed b13 clock from EdgeClk to RamClk (pg 12).3) Reset b4 with IRUN (pg 5).4) a3 Prom must be revision X.5) Added signal DevSerData (p. 9 and 11) to cause buffer parity generation on DevData to include ECC bits.IxIXGU9@pAGU>;GU1sGU!GU GUGUGMGMGAx>29"sp]MG2@ @K@tf0dKcQ>"sp@ta a ][ZnYQX5WUm9S4_nDQ#Pm&OQ"N41MK6J6IH"G#Fm%>p@A@tB#@Ps?44><;jNg12345678911121314151617101819ABCDEFGHI1-100101-20020pins: A16pins: B14pins: C22pins: D24 pins: ENote: The short vertical lines indicatefilter capacitor locations.PageD0DateRevDesignerProjectFileXEROXRDC LayoutJ. F. CameronRDCLayout.sil19CSL37-PIN MALE CONNECTOR15-PIN MALE CONNECTORS00S175S241S240S374S374S374S374S240S38HM7603S86S00S253S240S85S00S240S3225S09S20S175SPARES37425S09S04S374S64S11S169S74S86S280S175S138S280S08S04S519342293422934229342293422S280S32S02S00S74S163S163S257F93427F93427S175S74S74S257S163S163S174S174S74S74S00S00S10S04S32S00S00S241F93427S163S174SPARESPARES374S10S163S174S74S74S163S163S163S257S257S04SPARES240S174S5S09F93427S74S163S374S374F93427F93427F93427F93427S374S374S00S257S257S374S374S74S374S51S00S00F93427S04F93427F93427F93427S374S374S374S374S86S38S174S174S174S194S194S194S194S08S86S85SPARES00S241F93427F93427F93427F93427S163S16325S0925S09S240S51S64S175F9401S38S38S38PLATPLATPLAT7511475115751157/19/80S174Gc)z$$*:z$$*z$$+Wz$$+z$$)z$$(z$$(z$$'sz$$&z$$/:z$$/z$$0Wz$$0z$$1sz$$.z$$.z$$-z$$-z$$,sz$$4z$$5Wz$$5z$$6tz$$7z$$4;z$$3z$$3z$$2z$$2z$$:Wz$$:z$$;tz$$<z$$<z$$9z$$9;z$$8z$$8z$$7z$$?z$$@tz$$Az$$Az$$Bz$$?Wz$$>z$$>;z$$=z$$=z$$?$$@t$$A$$A$$B$$?W$$>$$>;$$=$$=$$:W$$:$$;t$$<$$<$$9$$9;$$8$$8$$7$$4$$5W$$5$$6t$$7$$4;$$3$$3$$2$$2$$/:$$/$$0W$$0$$1s$$.$$.$$-$$-$$,s$$)$$*:$$*$$+W$$+$$)$$($$($$'s$$&$$ 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